- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9002 > SL28PCIE50ALIT (Silicon Laboratories Inc)IC CLOCK PCIE GEN2 48QFN PDF資料下載
參數(shù)資料
| 型號： | SL28PCIE50ALIT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK PCIE GEN2 48QFN |
| 標準包裝： | 2,500 |
| 系列： | EProClock® |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | 時鐘，晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 100MHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應商設備封裝： | * |
| 包裝： | * |
SL28PCIe50
DOC#: SP-AP-0758 (Rev. AA)
Page 3 of 16
EProClock Programmable Technology
EProClock is the world’s first non-volatile programmable
clock. The EProClock technology allows board designer to
promptly achieve optimum compliance and clock signal
integrity; historically, attainable typically through device and/or
board redesigns.
EProClock technology can be configured through SMBus or
hard coded.
Features:
- > 4000 bits of configurations
- Can be configured through SMBus or hard coded
- Custom frequency sets
- Differential skew control on true or compliment or both
- Differential duty cycle control on true or compliment or both
- Differential amplitude control
- Differential and single-ended slew rate control
- Program Internal or External series resistor on single-ended
clocks
- Programmable different spread profiles
- Programmable modulation rates
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
42
CKPWRGD/PD#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled /this pin becomes a
real-time active low input for asserting power down (PD#)
43
VDD_SE1
PWR 3.3V Power Supply for CONF_SE1 clock
44
CONF_SE1
O, SE 3.3V, configurable single-ended clock
45
VSS_SE1
GND
Ground for CONFI_SE1 clock
46
CLKREQ#1*
I, PU
3.3V, active low input clock request to enable SRC1
(internal 100k-ohm internal pull-up)
47
CLKREQ#2*
I, PU
3.3V, active low input clock request to enable SRC2
(internal 100k-ohm internal pull-up)
48
OE_CONF_SE1
I
3.3V, active high input clock request to enable CONF_SE1
Pin No.
Name
Type
Description
Table 1. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1Start
1
Start
8:2
Slave address–7 bits
8:2
Slave address–7 bits
相關PDF資料 |
PDF描述 |
|---|---|
| VE-BTT-MY-F2 | CONVERTER MOD DC/DC 6.5V 50W |
| VI-J52-MZ-F3 | CONVERTER MOD DC/DC 15V 25W |
| VE-BTT-MY-F1 | CONVERTER MOD DC/DC 6.5V 50W |
| VI-J52-MZ-F2 | CONVERTER MOD DC/DC 15V 25W |
| VE-BT0-MY-F4 | CONVERTER MOD DC/DC 5V 50W |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SL28PCIe50LC | 功能描述:時鐘發(fā)生器及支持產品 PCIE family w/OE 25MHz Xtal input RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28PCIe50LCT | 功能描述:時鐘發(fā)生器及支持產品 PCIE family w/OE 25MHz Xtal input RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28PCIe50LI | 功能描述:時鐘發(fā)生器及支持產品 PCIE family w/OE 25MHz Xtal input RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28PCIe50LIT | 功能描述:時鐘發(fā)生器及支持產品 PCIE family w/OE 25MHz Xtal input RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28SRC01BZI | 功能描述:時鐘發(fā)生器及支持產品 PCIE Clk Gen Xin 14M -->1PCIE out Gen3 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購，3分鐘左右您將得到回復。