PC EProClock Programmable Technology<" />
參數(shù)資料
型號(hào): SL28EB719AZI
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 16/22頁(yè)
文件大?。?/td> 0K
描述: IC CLK CK505 TNLCK/TPCLF 48TSSOP
標(biāo)準(zhǔn)包裝: 39
系列: EProClock®
類型: 時(shí)鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 時(shí)鐘,晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:13
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 166.67MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
SL28EB719
DOC#: SP-AP-0005 (Rev. AB)
Page 3 of 22
PC EProClock Programmable Technology
PC EProClock is the world’s first non-volatile programmable
PC clock. The PC EProClock technology allows board
designer to promptly achieve optimum compliance and clock
signal integrity; historically, attainable typically through device
and/or board redesigns.
PC EProClock technology can be configured through SMBus
or hard coded.
Features:
- > 4000 bits of configurations
- Can be configured through SMBus or hard coded
- Custom frequency sets
- Differential skew control on true or compliment or both
- Differential duty cycle control on true or compliment or both
- Differential amplitude control
- Differential and single-ended slew rate control
- Program Internal or External series resistor on single-ended
clocks
- Program different spread profiles
- Program different spread modulation rate
35
SCLK
I
SMBus compatible SCLOCK
36
SDATA
I/O
SMBus compatible SDATA
37
CPU_STOP#*
I, PU
3.3V-tolerant input for stopping CPU outputs (internal 100K-ohm pull-up)
38
PCI_STOP#*
I, PU
3.3V-tolerant input for stopping PCI and SRC outputs (internal 100K-ohm
pull-up)
39
XOUT
O
25.00MHz Crystal output
40
XIN
I
25.00MHz Crystal input
41
GND_REF
GND
Ground for REF clock
42
25MHz
O
25MHz reference output clock
43
VDD_SUSPEND
PWR
3.3V Power Supply for REF clock and power to support WOL
44
CKPWRGD/WOL_STP#/PD#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled /
Asynchronous active low input pin that stops all outputs except free running
25MHz when WOL_EN = “1” (Byte 1 bit 1)
This pin becomes a real-time active low input for asserting power down (PD#)
when WOL_EN = “0” (Byte 1 bit 1).
45
VDD_14
PWR
3.3V Power supply for 14.318MHz clock
46
14.318M / FSC**
I/O, PD Fixed 14.318MHz clock output/3.3V-tolerant input for CPU frequency selection
(internal 100K-ohm pull-down)
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
47
GND_14
GND
Ground for 14.318MHz clock
48
NC
No Connect.
48-TSSOP Pin Definitions
Pin No.
Name
Type
Description
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