參數(shù)資料
型號: SL28548ALC-2T
元件分類: 時鐘產(chǎn)生/分配
英文描述: PROC SPECIFIC CLOCK GENERATOR, QCC64
封裝: 9 X 9 MM, 0.50 MM PITCH, ROHS COMPLIANT, QFN-64
文件頁數(shù): 30/32頁
文件大?。?/td> 685K
代理商: SL28548ALC-2T
SL28548-2
Rev 1.5 July 28, 2008
Page 7 of 32
32
SRCC11/ CR#_G
I/O,
DIF
Complementary 100 MHz differential serial reference clocks/3.3V CR#_G
Input Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
33
SRCT11/ CR#_H
I/O,
DIF
True 100 MHz differential serial reference clocks/3.3V CR#_H Input Selected
via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
34
SRCT10
O, DIF True 100 MHz differential serial reference clocks.
35
SRCC10
O, DIF Complementary 100 MHz differential serial reference clocks.
36
VDD_SRC_IO
PWR
3.3V-1.25V Power supply for outputs.
37
CPU_STOP#
I
3.3V-tolerant input for stopping CPU outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
38
PCI_STOP#
I
3.3V-tolerant input for stopping PCI and SRC outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
39
VDD_SRC
PWR
3.3V Power supply for SRC PLL.
40
SRCC6
O, DIF Complementary 100 MHz differential serial reference clocks.
41
SRCT6
O, DIF True 100 MHz differential serial reference clocks.
42
VSS_SRC
GND
Ground for outputs.
43
SRCC7/ CR#_E
I/O,
DIF
Complementary 100 MHz differential serial reference clocks/3.3V CR#_E
Input. Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
44
SRCT7/ CR#_F
I/O,
DIF
True 100 MHz differential serial reference clocks/3.3V CR#_FInput.
Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
45
VDD_SRC_IO
PWR
3.3V-1.25V power supply for outputs.
46
SRCC8 / CPUC2_ITP
O, DIF Selectable Complementary differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
47
SRCC8 / CPUC2_ITP
O, DIF Selectable True differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
48
NC
No connect.
49
VDD_CPU_IO
PWR
3.3V-1.25V Power supply for outputs.
50
CPUC1
O, DIF Complementary differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
51
CPUT1
O, DIF True differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
52
VSS_CPU
GND
Ground for outputs.
53
CPUC0
O, DIF Complementary differential CPU clock outputs.
54
CPUT0
O, DIF True differential CPU clock outputs.
55
VDD_CPU
PWR
3.3V Power supply for CPU PLL.
56
CKPWRGD / PWRDWN#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, GLCK_SEL and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
TSSOP Pin Definitions (continued)
Pin No.
Name
Type
Description
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SL28610BLI 功能描述:時鐘發(fā)生器及支持產(chǎn)品 AtomPoulsbo Handheld Embed.1.5V PCIe G1 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
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