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參數(shù)資料
| 型號： | SL15303EZIT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SSCG 1PLL 8TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | EProClock® |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | 時鐘，晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.25 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
Rev 2.0, October 11, 2010
Page 7 of 10
SL15303
External Components & Design Considerations
Typical Application Schematic
SL15303
XIN(3)
VDD(1)
XOUT(2)
SSCLK1 (7)
REFOUT (6)
133.333MHz +/-1.0% Spread
25.000MHz
2.2
μF
VSS(5)
REFOUT (4)
VDD=3.3V
25.000MHz
0.1
μF
VDDO=2.5V
VDDO (8)
Comments and Recommendations
Decoupling Capacitor: A dec
oupling capacitor of 0.1μF must be used between VDD and VSS on the pins 1 and 5.
Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the
VDD pin and to the GND via should be kept as short as possible Do not use vias between the decoupling capacitor
and the VDD pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the outputs
(SSCLK or REFCLK pins) and the load is over 1 inch. The nominal impedance of the SSCLK outpu
t is about 30 Ω.
Use 20 Ω resistor in series with the output to terminate 50Ω trace impedance and place 20 Ω resistor as close to the
SSCLK output as possible.
Crystal and Crystal Load: Use only parallel resonant fundamental crystals. DO NOT USE higher overtone crystals.
To meet the crystal initial accuracy specification (in ppm); the internal on-chip programmable capacitors PCin and
PCout must be programmed to match the crystal load requirement. These values are given by the formula below:
PCin(pF) =PCout(pF)= [(CL(pF) – Cp(pF)/2)] x 2
Where CL is crystal load capacitor as given by the crystal datasheet and Cp(pF) is the compensation factor for the
total parasitic capacitance at XIN or XOUT pin including PCB related parasitic capacitance.
As an example; if a crystal with CL=18pF is used and Cp=4pF, by using the above formula, PCin=PCout=[(18-(4/2)] x
2 = 32pF. Programming PCin and PCout to 32pF assures that this crystal sees an equivalent load of 18pF and no
other external crystal load capacitor is needed. Deviating from the crystal load specification could cause an increase
in frequency accuracy in ppm. Refer to the Table 5 for the recommended crystal specifications.
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