參數(shù)資料
型號: SL15100ZI
廠商: Silicon Laboratories Inc
文件頁數(shù): 14/16頁
文件大?。?/td> 0K
描述: IC CLOCK SSCG 1PLL 2CH 8TSSOP
標(biāo)準(zhǔn)包裝: 100
系列: EProClock®
類型: *
PLL: 帶旁路
輸入: 時(shí)鐘,晶體
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 200MHz
除法器/乘法器: 是/無
電源電壓: 2.25 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
Rev 1.8, August 10, 2007
Page 7 of 16
SL15100
Input Capacitance
CIN2
Pins 4 and 8
-
4
6
pF
Load Capacitance
CL
SSCLK/REFCLK , Pins 6 and 7
-
15
pF
AC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range 0 to +85 Deg C
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Input Frequency Range
FIN1
Crystal or Ceramic Resonator
8
-
48
MHz
Input Frequency Range
FIN2
External Clock
8
-
166
MHz
Output Frequency Range FOUT1
SSCLK
3
-
200
MHz
Output Frequency Range FOUT2
REFCLK, crystal or resonator input
0.25
-
48
MHz
Output Frequency Range FOUT3
REFCLK, clock input
0.25
-
166
MHz
Output Duty Cycle
DC1
SSCLK
45
50
55
%
Output Duty Cycle
DC2
REFCLK
45
50
55
%
Input Duty Cycle
DCIN
Clock Input, Pin 3
40
50
60
%
Output Rise/Fall Time
tr/f1
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
-
4.80
5.80
ns
Output Rise/Fall Time
tr/f2
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
-
2.60
3.10
ns
Output Rise/Fall Time
tr/f3
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
-
1.80
2.20
ns
Output Rise/Fall Time
tr/f4
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
-
1.40
1.70
ns
Output Rise/Fall Time
tr/f5
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
-
1.10
1.35
ns
Output Rise/Fall Time
tr/f6
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
-
0.90
1.10
ns
Output Rise/Fall Time
tr/f7
Programmable, VDD=2.5
CL=15pF, 20 to 80% of VDD
-
0.70
0.85
ns
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ1
CLKIN=SSCLK=166MHz,
2%Spread
REFCLK=Off
-
100
130
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ2
CLKIN=SSCLK=66MHz,
2%Spread, REFCLK=Off
-
110
140
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ3
CLKIN=SSCLK=33MHz,
2%Spread, REFCLK=Off
-
130
170
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ4
CLKIN=SSCLK=166MHz,
2%Spread REFCLK=On
-
110
140
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ5
CLKIN=SSCLK=66MHz,
2%Spread, REFCLK=On
-
115
150
ps
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