
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
200030B Skyworks Proprietary and Confidential Information Products and Product Information are Subject to Change Without Notice January 31, 2005
1
PRODUCT SUMMARY
SKY74702: Transmitter for CDMA Applications
Applications
CDMA phones in the cellular band:
CDMA-US
CDMA-Japan
Features
Serial bus interface control
Low power consumption in all operating modes
Image reject upconverter replaces external RF SAW filter
Transmit power control with 90 dB dynamic range
Variable gain RF block for improved in-band SNR
VHF VCO (external tank), 200 to 700 MHz
VHF VCO switching to increase the talk time of the radio
Two separate PLL synthesizers provide dual-loop, multi-band
operation and power-save mode for both standby and lower
frequency of operation
Fully programmable PLL dividers and selectable charge pump
currents for multi-VCO applications
Transmit puncture pin disables programmable portions of
device
RFLGA (40-pin, 6 x 6 x 1 mm) package with downset paddle
Description
The SKY74702 device is a single-supply, monolithic integrated
circuit. It is designed for use in single-mode Code Division
Multiple Access (CDMA) cellular voice/data applications including
extensions for CDMA-Japan.
The SKY74702 is a highly integrated superheterodyne transmitter
that incorporates the following components:
In-Phase and Quadrature (I/Q) modulator – accepts the analog I
and Q current outputs from the baseband analog processor and
converts them to Intermediate Frequency (IF) signals
Voltage Controlled Oscillator (VCO) and VHF synthesizer –
generates the LO signal for the quadrature modulator
UHF synthesizer – controls the UHF oscillator
Variable Gain Amplifier (VGA) – provides the variable output
power for CDMA systems
Image reject upconverter and power amplifier (PA) drivers
The signal enters the chip as a baseband I/Q signal, which is
upconverted by an I/Q quadrature modulator. The resulting signal
is fed through a VGA to provide variable output power. After
leaving the open collector output of the VGA, the signal enters a
switch matrix. This switch matrix allows the signal to be routed
through an external filter, or it can be filtered by the tuned
collector load and passed directly to the UHF image reject mixer.
The image reject mixer is internally connected to the PA driver.
The mixer driver combination has a variable gain control that can
be used to reduce the RF gain, which improves the in-band
Signal-to-Noise Ratio (SNR) at a lower output power. The PA
driver amplifies the RF signal to the appropriate level for the
desired output power. This is then filtered by a bandpass filter
and sent to an external PA to obtain the final rated output power
at the antenna.
The device package and pinout for the 40-pin RF Land Grid Array
(RFLGA) are shown in Figure 1. A block diagram of the SKY74702
is shown in Figure 2.
S304
VCC_IF
Q+
Q–
VCC_IQ_MOD
I+
I–
VCC_DIV
VCO_TANK+
VCO_TANK–
IREF
POT_IREF
31
30
29
28
27
26
25
24
23
22
21
V
V
V
V
S
U
R
L
U
V
V
V
V
N
P
I
I
V
N/C
N/C
N/C
N/C
VCC_BIAS_DIFF_DRV
CDMA_DRV_OUT
VCC_CDMA_DRV
TX_PUNCTURE
DATA
LATCH_ENABLE
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
Figure 1. SKY74702 Pinout – 40-Pin RFLGA Package
(Top View)