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參數(shù)資料
| 型號： | SK2111AXF |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 116K |
| 代理商： | SK2111AXF |
TEST AND MEASUREMENT PRODUCTS
1
www.semtech.com
Revision 4 / July 6, 2005
SK2111
Description
Features
Functional Block Diagram
SK2111 is a 1 to 10 data/clock distributor utilizing
LVDS (Low Voltage Differential Signaling) technology
for high speed operation. Data paths are fully differ-
ential from input-to-output for low noise generation
and low pulse width distortion. The design allows
connection of 1 input to all 10 outputs. LVDS I/O
enable high speed data transmission for point-to-point
interconnects. This device can be used as a high
speed differential 1 to 10 signal distribution / fanout
replacing multi-drop bus applications for higher speed
links with improved signal quality. It can also be
used for clock distribution up to 800 MHz.
The SK2111 accepts LVDS signal levels, LVPECL lev-
els directly or PECL with attenuation network resis-
tors. The inputs of SK2111 have an on-chip 100
termination resistors to minimize the component count.
The OE input is synchronous so that the outputs will
only be enabled/disabled when they are already in the
low state. This feature prevents generating any runt
clocks. The EDQUAD LQFP package has an exposed
heatslug which is connected to VEE substrate.
Pin Names
Pin Description
n
i
Pn
o
i
t
c
n
u
F
*
1
K
L
C
,
1
K
L
Cr
i
a
P
t
u
p
n
I
S
D
V
L
l
a
i
t
n
e
r
e
f
i
D
*
9
Q
,
*
0
Q
,
9
Q
,
0
Qs
t
u
p
t
u
O
S
D
V
L
l
a
i
t
n
e
r
e
f
i
D
V F
E
R
V
2
.
1
e
g
a
t
l
o
V
e
c
n
e
r
e
f
e
R
S
D
V
L
E
OS
O
M
C
V
L
/
L
T
V
L
t
u
p
n
I
e
l
b
a
n
E
t
u
p
t
u
O
Q0:Q9
Q0*:Q9*
10
Q
LEN
OE
VREF
1.2V
D
CLK1
CLK1*
100
1:10 Differential LVDS Clock Driver
E
OE
O9
Q
-
0
Q9
Q
-
0
Q
9
Q
-
0
Q
9
Q
-
0
Q9
Q
-
0
Q*
9
Q
-
*
0
Q*
9
Q
-
*
0
Q
*
9
Q
-
*
0
Q
*
9
Q
-
*
0
Q*
9
Q
-
*
0
Q
0W
O
LH
G
I
H
1n
Q*
n
Q
Truth Table
Supply Voltage Range: +3.0V to +3.6V
Part-to-part skew 75 ps (Max.)
Output channel-to-channel skew is 60 ps (Max.)
800 MHz minimum toggle frequency
Differential output voltage (DV
OUT) is 350 mV
(typical) with 100
termination load
LVDS receiver inputs accept LVPECL signals
On-chip 100
input termination resistor
Fast propagation delay of 500 ps (typical)
Receiver input threshold <
±100 mV
V
REF for LVDS single-ended input applications
ESD Protection of >4000V
Industrial Temperature Range: -40oC to +85oC
Available in 7mm x 7mm 32 Pin LQFP Package
with exposed heat slug
Conforms to ANSI/TIA/EIA-644 LVDS standard
VCC
Q7
Q7*
Q8
Q8*
Q9
Q9*
VCC
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VCC
Q2*
Q2
Q1*
Q1
Q0*
Q0
VCC
Q3
Q3*
Q4
Q4*
Q5
Q5*
Q6
Q6*
SK2111
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
NC
VCC
OE
V
REF
CLK1
CLK1*
VEE
NC
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