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參數(shù)資料
| 型號(hào)： | SK10EL34WD |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 10EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大小： | 82K |
| 代理商： | SK10EL34WD |
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SK10/100EL34W
Revision 1/November 7, 2001
HIGH-PERFORMANCE PRODUCTS
Notes:
1.
10EL circuits are designed to meet the DC specifications shown in the table after thermal equilibrium
has been established. The circuit is in a test socket or mounted on a printed circuit board and
transverse airflow greater than 500 lfpm is maintained. Outputs are terminated through a 50
W
resistor to VCC – 2.0V.
2.
100K circuits are designed to meet the DC specification shown in the table where transverse airflow
greater than 500 lfpm is maintained.
3.
Minimum input swing for which AC parameters guaranteed.
4.
CMR range is referenced to the most positive side of the differential input signal. Normal operation is
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP(min) and 1V. The lower end of the CMR range varies 1:1 with VEE and is equal to VEE + 2.0V.
5.
Voltages referenced to VCC = 0V, ECL configuration.
6.
For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data
Sheet.
7.
For part ordering description, see HPP Part Ordering Information Data Sheet.
AC Characteristics (continued)
CLK
Q0
Q1
Q2
EN*
Internal Clock
Disabled
Internal Clock
Enabled
The EN* signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its
assertion.
The internal dividers will maintain their state during the internal clock freeze and will return to
clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same
manner, time, and relationship as they would have had the EN* signal not been asserted.
Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
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| SK10ELT21W | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK10ELT21WD | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK10ELT21WDT | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK10ELT21WU | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK10EP111 | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver |
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