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參數(shù)資料
| 型號： | SK100E445PJ |
| 元件分類： | 計數(shù)移位寄存器 |
| 英文描述： | 100E SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 146K |
| 代理商： | SK100E445PJ |
8
www.semtech.com
HIGH-PER.ORMANCE PRODUCTS
SK10/100E445
Revision 2/April 10, 2002
Application Information (continued)
Perhaps the easiest way to delay the second clock relative
to the first is to take advantage of the differential clock
inputs on the E445. By connecting the clock for the
second E445 to the complimentary clock input pin, the
device will clock a half a clock period after the first E445
(Figure 4).
Utilizing this simple technique will raise
the potential conversion frequency up to 1.4 GHz. The
divide by eight clock of the second E445 should be
used to synchronize the parallel data to the rest of the
system as the parallel data of the two E445’s will no
longer by synchronized.
This skew problem between
the outputs can be worked around as the parallel
information will be static for eight more clock pulses.
Figure 4. Extended Frequency 1:8 Demultiplexer
Figure 5. Timing Diagram A: 1:8 Serial to Parallel Conversion
SERIAL
INPUT
DATA
SIN
SIN*
SOUT
SOUT*
E445a
Q3 Q2 Q1 Q0
Q7
Q6
Q5
Q4
SIN
SIN*
E445b
Q3
Q2
Q1 Q0
Q3
Q2
Q1
Q0
CLOCK
CLOCK*
CLOCK A
CLOCK B
Tpd CLK
to SOUT
PARALLEL OUTPUT DATA
800 ps
100 ps
1150 ps
Dn - 4
Dn - 3
Dn - 2
Dn - 1
Dn
Dn+1
Dn+2
Dn+3
Dn - 4
Dn - 3
Dn - 2
Dn - 1
Dn
Dn+1
Dn+2
Dn+3
CLK
SINA
Q0
SOUTb
Dn - 4
Dn - 3
Dn - 2
Dn - 1
Dn
Dn+1
SOUTa
CL/8a
CL/8b
CL/4a
CL/4b
Dn–4
Q1
Dn–3
Q2
Dn–2
Q3
Dn–1
Q4 (Q0 a)
Q5 (Q1 a)
Q6 (Q2 a)
Q7 (Q3 a)
Dn
Dn+1
Dn+2
Dn+3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SK100E445PJT | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:4-Bit Serial/Parallel Converter |
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| SK100EL01WD | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:4-Input OR / NOR |
| SK100EL01WDT | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:4-Input OR / NOR |
| SK100EL01WU | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:4-Input OR / NOR |
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