參數(shù)資料
型號(hào): SK100E131
廠商: Semtech Corporation
英文描述: 4-Bit d Flip-Flop(100K系列,帶差分輸出的4位D觸發(fā)器(屬高速ECL邏輯系列))
中文描述: 4位D觸發(fā)器(100K的系列,帶差分輸出的4位?觸發(fā)器(屬高速ECL邏輯系列))
文件頁(yè)數(shù): 1/4頁(yè)
文件大?。?/td> 112K
代理商: SK100E131
Description
Features
Functional Block Diagram
The SK10E/100E131 is a Quad master-slave D-type flip-
flop with differential outputs. Each flip-flop may be
clocked separately by holding Common Clock (CC) LOW
and using the Clock Enable (CE*) inputs for clocking.
Common clocking is achieved by holding the CE inputs
LOW and using CC to clock all four flip-flops. In this
case, the CE* inputs perform the function of controlling
the common clock to each flip-flop.
Individual asynchronous resets are provided (R).
Asynchronous set controls (S) are ganged together in
pairs, with the pairing chosen to reflect physical chip
symmetry.
Data enters the master when both CC and CE* are LOW,
and transfers to the slave when either CC or CE (or both)
go HIGH.
1100 MHz Minimum Toggle Frequency
Differential Outputs
Individual and Common Clocks
Individual Resets (asynchronous)
Paired Sets (asynchronous)
Extended 100E VEE Range of –4.2V to –5.5V
75K
Internal Input Pulldown Resistors
Fully Compatible with MC10E131 and
MC100E131
Specified Over Industrial Temperature Range:
–40
o
C to 85
o
C
ESD Protection of >4000V
Available in 28-pin PLCC Package
Q
Q
D
S
R
Q3
D3
CE3*
R3
D2
CE2*
R2
R1
S03
S12
CC
CE1*
D1
R0
CE0*
D0
Q3*
Q
Q
D
S
R
Q2
Q2*
Q
Q
D
S
R
Q1*
Q1
Q
Q
D
S
R
Q0*
Q0
PIN Description
!
"
!
"
$
!
Q2*
Q2
VCC
Q1*
Q1
Q0*
Q0
CE3*
D3
S12
VEE
CC
S03
D0
C
R
D
C
R
N
V
R
D
C
R
V
Q
Q
1
2
3
4
25
24
23
22
21
20
19
5
6
7
8
9
10
11
26
27
28
18
17
16
15
14
13
12
28 Lead PLCC
(Top View)
相關(guān)PDF資料
PDF描述
SK10E131PJT 4-Bit D Flip-Flop
SK10E131 4-Bit D Flip-Flop
SK10E131PJ 4-Bit D Flip-Flop
SK100E151 6-Bit D Register(100K系列,6位D寄存器(屬高速ECL邏輯系列))
SK10E151PJT 6-Bit D Register
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