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參數(shù)資料
| 型號(hào)： | SIP824ZEUDT-TR1 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | 5-Pin UP Reset Circuits with Watchdog Timer and Manual Reset |
| 中文描述： | 5引腳復(fù)位和看門狗定時(shí)器和手動(dòng)復(fù)位電路 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 55K |
| 代理商： | SIP824ZEUDT-TR1 |
SiP823/SiP824/SiP825
Vishay Siliconix
Document Number: 72397
S-41150—Rev. B, 14-Jun-04
www.vishay.com
3
SPECIFICATIONS
Test Conditions Unless Specified
Limits
Typ
b
Parameter
Symbol
T
A
=
40 C to 85 C, Typical Values @ T
A
= 25 C
Min
a
Max
a
Unit
Supply Voltage
V
CC
1
5.5
V
Supply Current (No Load)
I
CC
V
CC
= V
TH
+ 10%
10.0
A
T
A
= 25 C
3.0
RESET Threshold
V
TH
T
A
= 25 C
V
TH
1.5%
V
TH
1.5%
V
Threshold Hysteresis
V
TH(hys)
0.4
%V
TH
RESET Threshold
Temperature Coefficient
40
PPM/ C
V
OL
Sip82_L/M/J: V
CC
V
TH
, I
SINK
= 1.2 mA
0.5
RESET Output Voltage
Sip82_R/S/T/Y/Z: V
CC
V
TH
, I
SINK
= 0.5 mA
0.4
V
OH
V
CC
V
TH
, I
SOURCE
= 0.5 mA
0.8 V
CC
V
V
OL
Sip82_L/M/J: V
CC
V
TH
, I
SINK
= 1.2 mA
0.5
RESET Output Voltage
Sip82_R/S/T/Y/Z: V
CC
V
TH
, I
SINK
= 0.5 mA
0.4
V
OH
V
CC
V
TH
, I
SOURCE
= 0.5 mA
0.8 V
CC
V
CC
to RESET Delay
RESET Time-out Period
T
D1
T
D2
V
CC
= V
TH
100 mV
40
S
140
210
280
mS
Watchdog Input (SiP823/SiP824)
Watchdog Time-out Period
t
WD
1.12
1.76
2.40
S
W
D1
Pulse Width
t
WDI
V
IL
V
IL
= 0.4 V, V
IH
= 0.8 V
CC
50
nS
W
DI
Input Voltage
c
V
CC
= V
TH
+ 20%
0.7
V
V
IH
0.8 V
CC
W
DI
Input Current
I
IL
W
DI
= 0 V
15
8
A
I
IH
W
DI
= V
CC
= 5 V
8
15
Manual Reset Input (SiP823/SiP825)
MR Pulse Width
t
MR
1.0
S
MR Input Voltage
V
IL
V
CC
= V
TH
+ 20%
0.7
V
V
IH
0.8 V
CC
MR Noise Immunity
(Pulse Width with No RESET)
100
nS
MR to RESET Delay
t
MR
500
MR Pull-Up Resistance
80
120
k
Notes
a.
b.
c.
The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing.
W
DI
is internally serviced within the watchdog period if W
DI
is left unconnected.
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