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參數(shù)資料
| 型號： | SIP824LEUDT-TR1 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | 5-Pin UP Reset Circuits with Watchdog Timer and Manual Reset |
| 中文描述： | 5引腳復位和看門狗定時器和手動復位電路 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 55K |
| 代理商： | SIP824LEUDT-TR1 |
SiP823/SiP824/SiP825
Vishay Siliconix
Document Number: 72397
S-41150—Rev. B, 14-Jun-04
www.vishay.com
5
DETAILED DESCRIPTION
An active signal on a microprocessor ( P) RESET input starts
the P in a know state. The SiP823/SiP824/SiP825 P
supervisory circuits assert a RESET signal to prevent code
execution errors during power-up, power-down and brown-out
conditions.
The SiP823/SiP824/SiP825 also monitors the P’s health by
checking for problematic inactivity at its W
DI i
input.
RESET Output
A RESET will be asserted for the specified RESET time-out
period (t
D2
), if any of three conditions are present:
1) V
CC
drops below the threshold voltage (V
TH
)
2) The MR pin is pulled low
3) The watchdog timer does not detect a transition within the
watchdog interval (t
WD
) and the watchdog input is not left
floating.
The RESET output will remain asserted for the specified
time-out period (t
D2
) after:
1) V
CC
rises above the RESET threshold (V
TH
)
2) MR goes high.
Manual RESET Input
P based products often require a manual RESET capability,
which can be activated by manual intervention or external logic
circuitry.
A logic low at the MR pin of the SiP823/SiP824/SiP825 asserts
a RESET signal. RESET remains asserted while MR is low
and for a period (t
D2
) after it returns high.
MR has an internal 100-k pull-up resistor, so it can be left
floating when not activated. This input can be driven with
CMOS logic levels or with open drain devices. The input is
internally de-bounced to reject fast input transients.
Watchdog Input (SiP823/SiP824)
The SiP823/SiP824 have a watchdog input (WDI), that
monitors the P’s activity. If the P does not toggle the
watchdog input within the watchdog time-out period (t
WD
),
RESET is asserted. The internal RESET timer is cleared by
either a RESET pulse or by toggling WDI.
WDI detects pulses as short as 50 nS. While RESET is
asserted, the timer remains cleared. As soon as RESET is
released the timer starts counting (Figure 2).
The watchdog timer can be disabled by leaving WDI open or
by three stating the connected driver. As soon as the WDI input
is driven either high or low, the watchdog function resumes with
the watchdog timer set to zero.
WDI Input Current
The watchdog input pin (WDI) typically sources or sinks 8 A
when driven high or low.
As a result, the power dissipation at the WDI input is
independent of duty cycle. When the WDI pin is left floating or
tri-stated, the power supply current is less than 3 A.
Transient Rejection
The SiP823/SiP824/SiP825 family has good immunity for
negative going transients on the V
CC
line.
The smaller the duration of the transient, the larger the
amplitude can be without triggering RESET.
The “Transient Rejection” graph below shows the relation
between transient amplitude and allowable transient duration,
without triggering RESET.
The value on the horizontal scale represents the portion of the
amplitude of the transient that is exceeding the V
TH
level.
RESET Output State at Low V
DD
With V
CC
voltage on the level of MOS transistor thresholds
(
1.0 V), the RESET output of the SiP823/SiP824/SiP825
may become undefined. For outputs that are active low
(RESET), a resistor placed between RESET and GND on the
order of 100 k will ensure that the RESET output stays low
when the V
CC
drops below the MOS transistor threshold. In a
like manner, a resistor placed between RESET and V
CC
will
ensure the correct state for active high RESET outputs.
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