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參數(shù)資料
| 型號(hào)： | SiP2805 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | Low Power Consumption Current Mode Controller |
| 中文描述： | 低功耗電流模式控制器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 93K |
| 代理商： | SIP2805 |
SiP2800/01/02/03/04/05
Vishay Siliconix
New Product
www.vishay.com
6
Document Number: 72660
S-41623—Rev.C, 30-Aug-04
DETAILED PIN DESCRIPTION
COMP
COMP is the output of the Voltage Error Amplifier (VEA). The
VEAisalowoutputimpedanceoperationalamplifier,providing
the input to the PWM cycle-by-cycle current limit comparator.
As the SiP280X series of parts use a true operationalamplifier
for the VEA, the COMP terminal can both source and sink
current. To add flexibility to these parts, the VEA is internally
current limited, which allows OUT to be forced to zero duty
cycle by taking the COMP pin to GND.
The voltage on COMP is passed through an internal diode to
develop an offset voltage of approximately 0.6 V, and then
through a resistive divider with a gain of 0.606-V/V, before
being presented to the control input of the cycle-by-cycle
current limit comparator. Clamping the COMP pin to less than
the diode’s forward voltage (i.e.,
<
0.5 V) will command the
current loop to deliver 0 A, by holding the control input of the
cycle-by-cyclecurrentcomparatorat0 V. Similarly,thecurrent
loop will command the maximum inductor current on each
cycle when COMP is at 2.25 V or greater, which drives the
control input of the cycle-by-cycle current comparator to 1 V
(since [2.25 V -- 0.6 V]
×
0.606 V/V = 1 V).
The SiP280X series additionally features a built-in soft-start
function, which functions by clamping the output level of the
VEA to an internally generated voltage. This clamp will hold
COMP at a low voltage (V
COMP
≈
0 V) until V
CC
and V
REF
are
at their proper levels. When these levels are appropriate for
circuit operation, the internal voltage will begin rising, at the
rate of1 V/ms.This risingclamp levelallows thevoltage onthe
COMPpinto rise,which inturn allowsthe voltageatthecontrol
inputofthecycle-by-cyclecurrentcomparatortoincrease.The
maximum soft-start interval occurs under conditions requiring
full duty cycle (50% or 100%, depending upon the part type),
and is given by the time required for the voltage on the
cycle-by-cycle current comparator’s control inputto reach 1 V.
Since 1 V at the control input to the comparator requires that
the COMP pin be at 2.25 V, the maximum soft-start interval is
approximately 2.25 ms.
CS
Input to both the cycle-by-cycle and overcurrent fault current
sense
comparators.
The
comparator is the mechanism by which the VEA’s output
voltage commands the level of inductor or transformer current
during a given “on” interval, thereby regulating the overall
circuit’soutput.This comparatorforms theinnerloopofthetwo
loops used in current-mode regulation.
cycle-by-cycle
current
limit
The overcurrent comparator has a trip threshold that is 50%
higher than that of the cycle-by-cycle comparator.
normal operating conditions, this comparator will not trip: its
purpose is to provide enhanced protection of the power path
components during severe faults (e.g., a short circuit). If the
overcurrent comparator is tripped by a fault condition, it will
command the SiP280X to do a “full-cycle restart.” During this
restart,the powersupply willbe quickly driven tothe “off”state,
and willbe required to waitforfive milliseconds (typical)before
restarting. When the supply does restart, itwill do so using the
built-in soft-start function of the SiP280X.
Under
The SiP280X family incorporates internal leading-edge
blanking on the CS pin, to keep any spurious voltages on the
CS pin from reaching the comparator inputs during the 100-ns
interval immediately following the rising edge on OUT (for
example, voltages due to capacitive charging currents).
Because of this internal leading-edge blanking, many
applications require no external RC filter on the CS input.
Compared to circuits requiring the use of an external RC filter
circuit, leading-edge blanking provides a shorter effective CS
to OUT propagation delay.
FB
FB is the inverting input of the VEA. Internally compared
againstV
REF
/2 appearingon theVEA’s non-invertinginput. To
avoid stability problems, keep lead lengths to FB as short as
possible, and use good layout practices to minimize the stray
capacitances of components connected to this pin.
GND
The GND pin is both the reference ground and the power
ground for this part.
OUT
OUT is the output of a high-current driver capable of peak
currents in excess of
750 mA. OUT is therefore well suited
to driving the gates ofpowerMOSFETs. Thispin isspecifically
held lowwhen V
CC
is belowthe SiP280X’s UVLOthreshold,to
ensure a predictable system turn-on. Since the OUT pin is
internally connected to a low impedance CMOS buffer, it is
capable of rapid rail-to-rail transitions. This output topology
also mitigates the effects of undershoot and overshoot. For
this reason, external Schottky clamp diodes are generally not
required on this pin.
RC
RCis the oscillatorfrequency programming pin.F
OSC
is setby
the combination of R
T
and C
T
. The charging current for C
T
is
provided through R
T
, which is normally connected between
REF and the SiP280X RC pin. C
T
then connects from RC to
GND. Due to the high impedances encountered in low power
control circuits, this connection must be a short and quiet
return to GND (preferably by means of a dedicated signal
trace, separated from all other circuit functions).
The oscillator frequency for the SiP280X family of parts is
approximated by the following formulas:
For the SiP2800, SiP2801, SiP2802, and SiP2804:
D
F
OSC
≈
(1.5)/R
T
C
T
For the SiP2803 and SiP2805:
D
F
OSC
≈
(1.0)/R
T
C
T
Here R
T
is in ohms and C
T
is in farads.
More accurate formulas for F
OSC
are:
For the SiP2800, SiP2801, SiP2802 and SiP2804:
D
F
OSC
= 1/{[(C
T
+ C
STRAY
) x R
T
x 0.652] + [(C
T
+ C
STRAY
)
x R
DISCH
x 2.53] + T
DELAY
}
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