參數(shù)資料
型號: SiI3726CB
廠商: Silicon Image, Inc.
英文描述: SATA Port Multiplier
中文描述: SATA端口倍增器
文件頁數(shù): 20/41頁
文件大?。?/td> 375K
代理商: SII3726CB
SiI3726 SATA Port Multiplier
Data Sheet
Device Initialization
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0121-C1
20
Firmware must be downloaded into the SiI 3726 SATA Port Multiplier from a Serial EEPROM for normal operation.
The serial EEPROM is connected to pin numbers A9 (Serial Clock) and B9 (Serial Data).
Auto-Initialization from the EEPROM
EEPROM Specifications
The port multiplier requires an external 64 kByte (or two 64 kByte EEPROMs for double buffering) serial EEPROM
(400 KHz) memory device. When double buffering is used (for fail over purposes) the primary EEPROM address
must be set to “000” and the secondary EEPROM address must be set to “001”.
When powered-up, the port multiplier verifies the checksum in the primary EEPROM before loading the firmware.
If the checksum does not match, the port multiplier loads the firmware from the secondary EEPROM.
The firmware contained in the EEPROM is shown below:
Address
0x0000 – 0xFFED
Code to configure the SiI 3726
0xFFEC – 0xFFF3
System Information, may contain the Serial Number, must be an ASCII string (null
terminated)
0xFFF4 – 0xFFF7
Vendor ID and Chip ID 0x10953726
0xFFF8 – 0xFFFB
Firmware Revision
0xFFFC – 0xFFFF
Signature / CheckSum
Contents
The sequence of events is as follows:
1. System power-up
2. Code transfer from the EEPROM (I
2
C) to the SiI 3726 SATA Port Multiplier (boot)
3. The port multiplier starts operating under software control (normal operation)
EEPROM Read/Write Operations
The timing diagram for read or write operations is shown in Figure 3. The high-level timing for a random read or
write is shown in Figure 4. The high-level timing for a block transfer is shown in Figure 5.
EPR_SC
EPR_SD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Ack
Start
Stop
Figure 3: I
2
C Transfer Timing
A
A
A
A
EPR_SC
EPR_SD
EPR_SD
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
S
S
A
A
A
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
0
1
0
0
0
0
0
S
S
Control Byte
Address Hi
Address Lo
S
Control Byte
Random Read Command
Random Write Command
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