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參數(shù)資料
| 型號： | SII2024 |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | Fibre Channel Quad SerDes |
| 中文描述： | 光纖通道四的SerDes |
| 文件頁數(shù)： | 2/2頁 |
| 文件大?。?/td> | 983K |
| 代理商： | SII2024 |
2002 Silicon Image, Inc. All rights reserved. Silicon Image, the Silicon Image logo, MSL, SiI, SiI 2024, SATALink
and PanelLink are trademarks or registered trademarks of Silicon Image, Inc. in the United States and other
countries. Product specifications are subject to change without notice. Printed in the U.S.A. 9/02 SiI-PB-0029
Silicon Image, Inc.
1060 E. Arques, Sunnyvale, CA 94085
T 408.616.4000 F 408.830.9530
www.siliconimage.com
SiI 2024 Features
Fibre Channel SerDes
General
Fibre Channel-compliant
Multi-rate: 1.0625 Gbps and
2.125 Gbps
Four independent channels
Advanced-power supply filtering
Low Power
Single 1.8V supply for core circuits
and 2.5V supply for parallel I/O
Power dissipation: 250 mW per
channel
Cost Effective
Standard CMOS technology
Plastic 324-pin PBGA
Parallel I/O Interface
10-bit interface with DDR for
2.125 Gbps mode
Flexibility of using reference clock
(REFCLK) instead of transmit byte
clocks (TBC) in “noisy” environments
Separate TBC for latching parallel
input data
SSTL_2 and High-Speed Parallel
Interface (HSPI)-compliant
Highly Reliable Serial
Interface
Individually selectable Tx and Rx
data rates per channel
Selectable pre-emphasis control
Selectable Tx swing control
Low-transmit jitter design
On-chip termination resistor
Proven Technology
MSL
TM
-based technology proven
with PanelLink
ICs for the PC and
CE markets (2-5 Gbps, over 30M
units shipped)
Robust design for "noisy"
environments
Serializer
REF_LOCK
TxD
TBC
REFCLK
Tx_RATE
Rx+
Rx-
Rx_LOS
FIFO
Si
I
2024
Sampler
V
V
T
T
T
T
T
Tx+
Tx-
10
EWRAP
COM_DET
RxD
Rx
PLL
Tx
PLL
10
10
SSTL CTRL
CTRL
JTAG CTRL
T
T
T
E
Mux
Mux
Byte
Sync
1.0625/2.125 Gbps
transmit signal
1.0625/2.125 Gbps
receive signal
Rx_RATE
RBC_SYNC
RBC[0:1]
Deserializer
Part Number - SiI2024CB324
Si
I
2024
Fibre Channel Quad SerDes
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