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參數(shù)資料
| 型號(hào)： | SII2022 |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | Fibre Channel SerDes |
| 中文描述： | 光纖通道SERDES |
| 文件頁數(shù)： | 2/2頁 |
| 文件大?。?/td> | 984K |
| 代理商： | SII2022 |
2002 Silicon Image, Inc.All rights reserved. Silicon Image, the Silicon Image logo, MSL, SiI, SiI 2022, SiI 2023,
and PanelLink are trademarks or registered trademarks of Silicon Image, Inc. in the United States and other
countries. Product specifications are subject to change without notice. Printed in the U.S.A. 6/02 SiI-PB-0028
Silicon Image, Inc.
1060 E. Arques, Sunnyvale, CA 94085
T 408.616.4000 F 408.830.9530
www.siliconimage.com
SiI 2022 Features
Fibre Channel SerDes
General
Fibre Channel-compliant
Multi-rate: 1.0625 Gbps and
2.125 Gbps
Low Power
Single 3.3V supply for core circuits
and high-speed I/O
Power dissipation: 450 mW
Cost Effective
Standard CMOS technology
Compact 64-pin, 14x14mm MQFP
(Metric Quad Flat Pack)
Narrow Parallel I/O
Interface
10-bit interface with DDR for
2.125 Gbps mode
SSTL_2 and High-Speed Parallel
Interface (HSPI)-compliant
Separate transmit byte clock (TBC)
for latching parallel input data
Highly Reliable Serial
Interface
Separately selectable Tx and Rx
data rates
Very-low-jitter PLL: 3.3 ps (random
jitter),32 ps (deterministic jitter)
Variable pre-emphasis control
Variable on-chip termination resistor
Full ESD tolerance to 2 kV
Proven Technology
MSL
TM
-based technology proven
with PanelLink
ICs for the PC and
CE markets (2-5 Gbps, over 30M
units shipped)
Robust design for "noisy"
environments
Serializer
Sampler
Tx[0:9]
Tx_RATE
TBC
Rx[0:9]
Tx+
Tx-
Rx+
Rx-
1.0625/2.125 Gbps
transmit signal
1.0625/2.125 Gbps
receive signal
Byte
Sync
C
E
E
Data
Output
Input
Latch
Deserializer
Tx
PLL
L
REFCLK[0:1]
RBC_SYNC
Rx_RATE
RBC[0:1]
R
Rx
PLL
Si
I
2022
Part Number - SiI2022CM64
Si
I
2022
Fibre Channel SerDes
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