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參數(shù)資料
| 型號： | SII141B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Box-shaped pin header, Discrete wire crimping connection, Discrete wire connectors; HRS No: 536-0101-9 00; No. of Positions: 2; Connector Type: Board mounting; Contact Gender: Male; Contact Spacing (mm): 1.25; Terminal Pitch (mm): 1.25; PCB Mount Type: Through-hole; Current Rating(Amps)(Max.): 1; Contact Mating Area Plating: Tin; Operating Temperature Range (degrees C): -35 to 85; General Description: Header; Straight; Single row |
| 中文描述： | 精工141B章PanelLink數(shù)字接收機(jī) |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 84K |
| 代理商： | SII141B |
Subject to Change without Notice
SiI 141B PanelLink
Digital Receiver
General Description
The SiI 141B uses PanelLink Digital technology to support displays
ranging from VGA to High Refresh XGA (25-86 MHz), which is ideal for LCD
desktop monitor applications. With a flexible single or dual pixel out interface
and selectable output drive, the SiI 141B receiver supports up to true color
panels (24 bit/pixel, 16.7M colors) in 1 pixel/clock mode (18 bit/pixel in 2
pixel/clock mode). PanelLink also features an inter-pair skew tolerance up to
1 full input clock cycle. The SiI 141B is pin for pin compatible with the SiI
141 but incorporates a number of enhancements. These include an
improved jitter tolerant PLL design, new HSYNC filter and power down when
the clock is inactive. All PanelLink products are designed on a scaleable
CMOS architecture to support future performance requirements while
maintaining the same logical interface. System designers can be assured
that the interface will be fixed through a number of technology and
performance generations.
PanelLink Digital technology simplifies PC design by resolving many of
the system level issues associated with high-speed digital design, providing
the system designer with a digital interface solution that is quicker to market
and lower in cost.
SiI 141B Pin Diagram
May 2001
Features
Scaleable Bandwidth: 25-86 MHz (VGA to High
Refresh XGA)
Low Power: 3.3V core operation & power-down mode
Automatic power down when clock is inactive
High Skew Tolerance: 1 full input clock cycle (15ns at
65 MHz)
Pin-compatible with Si
I
101, Si
I
141
Sync Detect: for Plug & Display “Hot Plugging”
Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
Compliant with DVI 1.0 (DVI is backwards compatible
with VESA P&D
and DFP)
1
SiI141B
80-Pin TQFP
(Top View)
PD
2
PDO
3
OGND
4
PIXS
5
DFO
6
SCDT
7
CTL1
8
CTL2
9
CTL3
10
GND
11
HSYNC
12
OGND
13
VSYNC
14
OVCC
15
Q0
16
Q
2
Q
2
Q
2
Q
2
Q
2
O
2
Q
2
O
2
Q
2
Q
3
Q
3
Q
3
Q
3
Q
3
Q
3
56
Q30
55
Q29
54
Q28
53
Q27
52
Q26
51
VCC
50
Q25
49
OVCC
48
Q24
47
OGND
46
Q23
45
Q22
44
Q21
43
Q20
42
DE
41
Q31
O
8
S
7
P
7
P
7
E
7
H
7
R
7
R
7
A
7
R
7
R
7
A
6
R
6
R
6
A
6
R
6
8-bit Channel 0 Data
1-pixel/clock
24-bit Input Data for 1-pixel/clock mode
DIFFERENTIAL SIGNAL
O
3
8-bit Channel 1 Data
1-pixel/clock
MISC.
G
P
C
C
Q1
17
Q2
18
Q3
19
Q4
20
G
3
Q
3
V
3
Q
4
60
Q34
59
Q33
58
Q32
57
Q35
R
6
A
6
G
6
V
6
8-bit Channel 2 Data
1-pixel/clock
6
D
6-bit Even Channel 2
Data 2-pixel/clock
6-bit Even Channel 1
Data 2-pixel/clock
6-bit Odd Channel 0
Data 2-pixel/clock
6
D
6
D
18-bit Even Data for 2-pixel/clock mode
1
RESERVED
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