參數(shù)資料
型號(hào): Si9139DG-2218
廠商: Vishay Intertechnology,Inc.
英文描述: Multi-Output, Individual On/Off Control Power-Supply Controller
中文描述: 多輸出,單獨(dú)開(kāi)/關(guān)控制電源控制器
文件頁(yè)數(shù): 17/17頁(yè)
文件大?。?/td> 162K
代理商: SI9139DG-2218
Si9139
Vishay Siliconix
New Product
Document Number: 71841
S-22317
Rev. A, 16-Dec-02
www.vishay.com
17
DESCRIPTION OF OPERATION (CONT’D)
Auxiliary Converter C Normal Operation: Boost Mode
The auxiliary converter may be operated in boost mode as
shown in Figure 1.B when operating from a 5 V
supply voltage. This ability reduces the component count of
the converter and provides a high efficiency output voltage of
in the range of 6 V to 20 V at up to10 W of power. Operation
is similar to the buck-boost mode described above.
10% input
Auxiliary Converter C Normal Operation: Buck Mode
The auxiliary converter may also be operated in buck mode as
shown in Figure 1.C when operating from a 5 V
supply voltage. This ability reduces the component count of
the converter and provides a high efficiency output voltage of
in the range of 1.24 V to 2.1 V with 1 W of power. Operation
is similar to the buck-boost mode described above.
10% input
Auxiliary Converter C Current Limit
Similar to the buck converter; when the voltage across pin
CSP and pin CSN exceeds 360-mV typical, the two MOSFETs
will be turned off regardless of the input and output conditions.
Grounding:
There are two separate grounds on the Si9139, analog signal
ground (GND) and power ground (PGND). The purpose of two
separate grounds is to prevent the high currents on the power
devices (both external and internal) from interfering with the
analog signals. The internal components of Si9139 have their
grounds tied (internally) together. These two grounds are then
tied together (externally) at a single point, to ensure Si9139
noise immunity.
This separation of grounds should be maintained in the
external circuitry, with the power ground of all power devices
being returned directly to the input capacitors, and the small
signal ground being returned to the GND pin of Si9139.
RESET Handler
The power-good monitor generates a system RESET signal.
At first power-up (ON
A/B
going high), RESET is held low until
the A and B outputs are in regulation and beyond the UVLO
timer. At this point, an internal timer begins counting oscillator
pulses and RESET continues to be held low until 32,000
cycles have elapsed. After this timeout period, 107 ms @
300 kHz, RESET is actively pulled up to V
L
, when the
recommended 20-k resistor to V
L
is on the RESET pin.
Output Overvoltage Protection
The A and B SMPS outputs are monitored for overvoltage. If
either output is more than 10% above the nominal regulation
point, all low-side gate drivers are latched high until ON
A
and
ON
B
are
toggled. This action turns on the synchronous
rectifier MOSFETs with a 100% duty cycle, in turn rapidly
discharging the output capacitors and forcing all SMPS
outputs to ground.
Output Undervoltage Protection
In Si9139, each of the A and B SMPS outputs has an
undervoltage protection circuit that is activated 6,144 clock
cycles (20.48 ms) after the SMPS is enabled. If either SMPS
output is typically under 70% of the nominal value, all SMPSs
are latched off and their outputs are clamped to ground by the
synchronous rectifier MOSFETs. The SMPS will not restart
until both ON
A
and ON
B
are toggled.
Stability:
Buck Converters:
In order to simplify designs, the A and B supplies do not require
external frequency compensation. Meanwhile, it achieves
excellent regulation and efficiency. The converters are current
mode control, with a bandwidth substantially higher than the
LC tank dominant pole frequency of the output filter. To ensure
stability, the minimum capacitance and maximum ESR values
are:
C
LOAD
V
REF
2
xV
OUT
x
R
CS
x
BW
ESR
V
OUT
x R
cs
V
REF
where V
REF
= 3.3 V, V
OUT
is the output voltage (A or B), Rcs
is the current sensing resistor in ohms and BW = 50 khz. With
the components specified in the application circuit (L = 10 H,
R
CS
= 0.02 , C
OUT
= 330 F, ESR approximately 0.1
converter has a bandwidth of approximately 50 kHz, with
minimum phase margin of 65 , and dc gain above 50 dB.
, the
Other Outputs
The Si9139 also provides a 3.3-V reference which can be
externally loaded up to 1 mA, as well as, a 5-V LDO output
which can be loaded up to 30 mA, or even more depending on
the system application. For stability, the 3.3-V reference output
requires a 1- F capacitor, and the 5-V LDO output requires a
10- F capacitor.
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