參數(shù)資料
型號: SI9124DQ-T1
廠商: Vishay Intertechnology,Inc.
元件分類: DC/DC變換器
英文描述: 500-kHz Push-Pull DC-DC Converter With Integrated Secondary Synchronous Rectification Control
中文描述: 500千赫推挽式直流與集成的次級同步整流控制DC轉(zhuǎn)換器
文件頁數(shù): 10/16頁
文件大?。?/td> 175K
代理商: SI9124DQ-T1
Si9124
Vishay Siliconix
New Product
www.vishay.com
10
Document Number: 72099
S-03638—Rev. B, 20-Mar-03
Care should be taken to control the operating time using the
internal preregulator to prevent excessive power dissipation in
the IC. The use of an external dropping resistor connected in
series with the V
IN
pin to drop the voltage during start up is
recommended. The value of R
EXT
is selected to drop the input
voltage to the IC under worst case conditions thereby
dissipating power in the resistor, instead of the IC. If the supply
output is shorted and the auxiliary winding does not provide the
V
CC
current, then continuous soft start cycles will occur. The
average power in the IC during start-up where the hiccup
operation would be performed continuously is given by:
Power(IC)
V
IN
t
1
I
CC2
t
2
I
CC4
I
CC5
I
SEC_SYNC
t
1
t
2
Power R
EXT
V
ID
t
1
I
CC2
t
2
I
CC4
I
CC5
I
SEC_SYNC
t
1
t
2
where V
ID
V
INEXT
V
IN
where I
CC2
is the non-switching supply current, I
CC4
and I
CC5
are the supply current while switching, and I
SEC_SYNC
is the
average current out of the SEC_SYNC pin, and t
1
and t
2
are
defined in
Figure 4
.
After the feedback voltage from the secondary overrides the
internal pre-regulator, no current flows through R
EXT
. An
example of the feedback circuitry is shown in Figure 15.
The SS
pin has a predictable +1.25-mV/ C temperature
coefficient and can be used to continuously monitor the
junction temperature of the IC for a given power dissipation.
Reference
The reference voltage of Si9124 is set at 3.3 V. The reference
voltage should be de-coupled externally with a 0.1
μ
F
capacitor. The V
REF
voltage is 0 V in shutdown mode and has
50-mA source capability.
Voltage Mode PWM Operation
Under normal load conditions, the IC operates in voltage mode
and generates a fixed frequency pulse-width modulated signal
to the drivers. Duty cycle is controlled over a wide range to
maintain the output voltage under line and load variation.
Voltage feed-forward is also included to improve line regulation
and transient response. In the push-pull topology requiring
isolation between output and input, the reference voltage and
error amplifier must be supplied externally, usually on the
secondary side.
The error information is usually passed to the power controller
through an opto-coupling device for isolation. The error
information enters the IC via pin EP and where 0 V results in
the maximum duty cycle, whilst 2 V represents minimum duty
cycle. The EP error signal is gained up by -2.2X via an
inverting amplifier and compared against the internal ramp
generator. The relationship between Duty Cycle and V
EP
is
shown in the Typical Characteristic section, Duty Cycle vs. V
EP
at 25 C , page 12.
Voltage feed-forward is implemented by taking the attenuated
V
INEXT
signal at V
INDET
to directly modulate he duty cycle. This
relationship is shown in the Typical Characteristic section,
Duty Cycle vs. V
INDET
,
page 12. The response time to line
transients is very short since the PWM duty cycle is charged
directly without having to go through the error amplifier
feedback loop. At start-up, i.e., once V
CC
is greater than
V
UVLO
,
switching is initiated under soft-start control which
increases maximum attainable switch on-time linearly over the
soft-start period. Start-up from a V
INDET
power down,
over-temperature, or over current is also initiated under
soft-start control.
Push-Pull
Sequence
and Synchronous Rectification Timing
The PWM signal generated within the IC controls the OUT
A
and OUT
B
drivers on alternate cycles. A period of inactivity
always results after initiation of the soft-start cycle until the
soft-start voltage reaches approximately 2 V
be
and PWM
generated switching begins. The timing and coordination of
the drives to the primary and secondary stages is very
important and the relationships are shown in Figure 3. It is
essential to avoid the situation where both of the secondary
MOSFETs are on when either the OUT
A
or OUT
B
switches are
active. In this situation the transformer would effectively be
presented with a short across the output. To avoid this a timing
signal is made available which is ahead of the primary drive
outputs by 80 ns.
Primary MOSFET Drivers
The drive voltage for the primary MOSFETs is provided directly
from the V
CC
and V
CC2
supply. The switch gate drive signals
OUT
A
and OUT
B
are shown in Figure 3. The drive currents for
the primary side MOSFETs is supplied from the V
CC
and V
CC2
supply and can influence start up conditions.
Secondary Synchronization Driver
The secondary side MOSFETs are driven by the SEC_SYNC
output via a pulse transformer and gate driver circuits. The
time relationships are shown in Figure 3. Logic circuitry on the
secondary side is required to align the synchronous rectifier
gate drive with the primary drive. The current supplied to the
pulse transformer is drawn from V
CC
.
Oscillator
The oscillator is designed to operate at a frequencies up to 500
kHz. The 500-kHz operating frequency allows the converter to
minimize the inductor and capacitor size, improving the power
density of the converter. The oscillator and therefore the
switching frequency is programmable by a resistor on the
R
OSC
pin. The relationship is shown in the Typical
Characteristics, F
OSC
vs. R
OSC
.
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