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參數(shù)資料
| 型號(hào)： | SI9123 |
| 廠商： | Vishay Intertechnology,Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | 500-kHz Half-Bridge DC-DC Converter With Integrated Secondary Synchronous Rectification Control |
| 中文描述： | 500千赫半橋型DC - DC與集成的次級(jí)同步整流控制轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 10/16頁(yè) |
| 文件大小： | 181K |
| 代理商： | SI9123 |
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Si9123
Vishay Siliconix
New Product
www.vishay.com
10
Document Number: 72098
S-03639—Rev. B, 20-Mar-03
Care should be taken to control the operating time using the
internal pre-regulator to prevent excessive power dissipation in
the IC. The use of an external dropping resistor connected in
series with the V
IN
pin to drop the voltage during start up is
recommended. The value of R
EXT
is selected to drop the input
voltage to the IC under worst case conditions thereby
dissipating power in the resistor, instead of the IC. If the supply
output is shorted and the auxiliary winding does not provide the
V
CC
current, then continuous soft-start cycles will occur. The
average power in the IC during start-up where the hiccup
operation would be performed continuously is given by:
Power(IC)
V
IN
t
1
I
CC2
t
2
I
CC4
I
SEC_SYNC
t
1
t
2
Power R
EXT
V
INEXT
V
IN
t
1
I
CC2
t
2
I
CC4
I
SEC_SYNC
t
1
t
2
where I
CC2
is the non-switching supply current, I
CC4
is the
supply current while switching, I
SEC_SYNC
is the average
current out of the SEC_SYNC pin, and t
1
and t
2
are defined in
Figure 4
.
After the feedback voltage from the secondary overrides the
internal pre-regulator, no current flows through R
EXT
. An
example of the feedback circuitry is shown in
Figure 15
.
The SS
pin has a predictable +1.25-mV/ C temperature
coefficient and can be used to continuously monitor the
junction temperature of the IC for a given power dissipation.
Reference
The reference voltage of Si9123 is set at 3.3 V. The reference
voltage should be de-coupled externally with a 0.1
capacitor and has 50-mA source capability. The REF pin
voltage is 0 V in shutdown mode.
F
Voltage Mode PWM Operation
Under normal load conditions, the IC operates in voltage mode
and generates a fixed frequency pulse-width modulated signal
to the drivers. Duty cycle is controlled over a wide range to
maintain the output voltage under line and load variation.
Voltage feed-forward is also included to improve line regulation
and transient response. In the half-bridge topology requiring
error amplifier are supplied externally, usually on the
secondary side.
The output error signal is usually passed to the power
converter through an opto-coupling device for isolation. The
error information enters the IC via pin EP and where 0 V results
in the maximum duty cycle, whilst 2 V represents minimum
duty cycle. The EP error signal is gained up by -2.2X via an
inverting amplifier and compared against the internal ramp
generator. The relationship between Duty Cycle and V
EP
is
shown in the Typical Characteristic section,
Duty Cycle vs. V
EP
25 C
, page 12.
Voltage feed-forward is implemented by taking the attenuated
V
INEXT
signal at V
INDET
to directly modulate the duty cycle.
This relationship is shown in the Typical Characteristic section,
Duty Cycle vs. V
INDET
,
page 12. The response time to line
transients is very short since the PWM duty cycle is changed
directly without having to go through the error amplifier
feedback loop. At start-up, i.e., once V
CC
is greater than
V
UVLO
, switching is initiated under soft-start control which
increases the maximum attainable switch on-time linearly over
the soft-start period. Start-up from a V
INDET
power down,
over-temperature, or over current is also initiated under
soft-start control.
Half-Bridge and Synchronous Rectification Timing
Sequence
The PWM signal generated within the IC controls the low and
high-side bridge drivers on alternate cycles. A period of
inactivity always results after initiation of the soft-start cycle
until the soft-start voltage reaches approximately 2 Vbe and
PWM generated switching begins. The first bridge driver to
switch is always the low-side, D
L
as this allows charging of the
high-side boost capacitor. The timing and coordination of the
drives to the primary and secondary stages is very important
and the relationships are shown in
Figure 3
. It is essential to
avoid the situation where both of the secondary MOSFETs are
on when either the high or the low-side switch are active. In this
situation the transformer would effectively be presented with a
short across the output. The SEC_SYNC timing signal is set
to be ahead of the primary drive outputs by 50 - 80 ns.
Primary High- and Low-Side MOSFET Drivers
The drive voltage for the low-side MOSFET switch is provided
directly from the V
CC
supply. The high-side MOSFET however
requires the gate voltage to be enhanced above V
IN
. This is
achieved by bootstrapping the V
CC
voltage onto the L
X
voltage
(the high-side MOSFET source). In order to provide the
bootstrapping an external diode and capacitor are required as
shown on the application schematic. The capacitor will charge
up after the low-side driver has turned on. The driver signals
D
H
and D
L
are shown in
Figure 3
. The drive currents for the
primary side MOSFETs is supplied from the V
CC
supply and
can influence start up conditions.
Secondary Synchronization Driver
The secondary side MOSFETs are driven by the SEC_SYNC
output via a pulse transformer and gate driver circuits. The
time relationships are shown in
Figure 3
. Logic circuitry on the
secondary side is required to align the synchronous rectifier
gate drive with the primary drive. The current supplied to the
pulse transformer is drawn from V
CC
.
Oscillator
The oscillator is designed to operate at a frequencies up to
500 kHz. The 500-kHz operating frequency allows the
converter to minimize the inductor and capacitor size,
improving the power density of the converter. The oscillator
and therefore the switching frequency is programmable by a
resistor on the R
OSC
pin. The relationship is shown in the
Typical Characteristics, F
OSC
vs. R
OSC
.
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