Si5367
Rev. 0.5
71
70
A2_SS
ILVCMOS
Serial Port Address/Slave Select.
In I2C microprocessor control mode (CMODE = 0), this
pin functions as a hardware controlled address bit. The
I2C address is 1101 [A2][A1][A0.]
In SPI microprocessor control mode (CMODE = 1), this
pin functions as the slave select input.
This pin has a weak pull-down.
71
SDI
I
LVCMOS
Serial Data In.
In SPI microprocessor control mode (CMODE = 1), this
pin functions as the serial data input.
In I2C microprocessor control mode (CMODE = 0), this
pin is ignored.
This pin has a weak pull-down.
77
78
CKOUT3+
CKOUT3–
OMULTI
Clock Output 3.
Differential clock output. Output signal format is selected
by SFOUT3_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
82
83
CKOUT1–
CKOUT1+
OMULTI
Clock Output 1.
Differential clock output. Output signal format is selected
by SFOUT1_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
87
88
CKOUT5–
CKOUT5+
OMULTI
Clock Output 5.
Differential clock output. Output signal format is selected
by SFOUT5_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
90
CMODE
I
LVCMOS
Control Mode.
Selects I2C or SPI control mode for the device.
0=I2C Control Mode.
1 = SPI Control Mode.
This pin must be tied high or low.
92
93
CKOUT2+
CKOUT2–
OMULTI
Clock Output 2.
Differential clock output. Output signal format is selected
by SFOUT2_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
Table 11. Si5367 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.