- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8970 > SI5338N-A-GM (Silicon Laboratories Inc)IC CLK GEN I2C BUS PROG 24QFN PDF資料下載
參數(shù)資料
| 型號： | SI5338N-A-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 10/44頁 |
| 文件大小： | 0K |
| 描述： | IC CLK GEN I2C BUS PROG 24QFN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 系列： | MultiSynth™ |
| 類型： | * |
| PLL： | 是 |
| 輸入： | CML，HCSL，HSCL，LVDS，LVPECL，晶體 |
| 輸出： | CMOS，HCSL. HSTL. LVDS. LVPECL. SSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 700MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN（4x4） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
Si5338
18
Rev. 1.3
3.2. Input Stage
The input stage supports four inputs. Two are used as
the clock inputs to the synthesis stage, and the other
two are used as feedback inputs for zero delay or
external feedback mode. In cases where external
feedback is not required, all four inputs are available to
the synthesis stage. The reference selector selects one
of the inputs as the reference to the synthesis stage.
The input configuration is selectable through the IC
interface. The input MUXes are set automatically in
ClockBuilder
Desktop
(see
Desktop Software”). For information on setting the input
MUXs manually, see the Si5338 Reference Manual:
Configuring the Si5338 without ClockBuilder Desktop.
Figure 2. Input Stage
IN1/IN2 and IN5/IN6 are differential inputs capable of
accepting
clock
rates
from
5
to
710 MHz.
The
differential inputs are capable of interfacing to multiple
signals, such as LVPECL, LVDS, HSCT, HCSL, and
CML. Differential signals must be ac-coupled as shown
in Figure 3. A termination resistor of 100
placed close
to the input pins is also required. Refer to Table 6 for
signal voltage limits.
Figure 3. Interfacing Differential and Single-
Ended Signals to the Si5338
IN3 and IN4 accept single-ended signals from 5 MHz to
200 MHz. The single-ended inputs are internally ac-
coupled; so, they can accept a wide variety of signals
without requiring a specific dc level. The input signal
only needs to meet a minimum voltage swing and must
not exceed a maximum VIH or a minimum VIL. Refer to
Table 6 for signal voltage limits. A typical single-ended
connection
is
shown
in
For
additional
termination options, refer to “AN408: Termination
Options
for
Any-Frequency,
Any-Output
Clock
Generators
and
Clock
Buffers—Si5338,
Si5334,
Si5330”.
For free-run operation, the internal oscillator can
operate from a low-frequency fundamental mode crystal
(XTAL) with a resonant frequency between 8 and
30 MHz. A crystal can easily be connected to pins IN1
and IN2 without external components as shown in
are guaranteed to work with the Si5338.
Figure 4. Connecting an XTAL to the Si5338
Refer to “AN360: Crystal Selection Guide for Si533x/5x
Devices” for information on the crystal selection.
3.2.1. Loss-of-Signal (LOS) Alarm Detectors
There are two LOS detectors: LOS_CLKIN and
LOS_FDBK. These detectors are tied to the outputs of
the P1 and P2 frequency dividers, which are always
enabled. See "3.6. Status Indicators" on page 23 for
details on the alarm indicators. These alarms are used
during programming to ensure that a valid input clock is
detected. The input MUXs are set automatically in
ClockBuilder Desktop (see the Si5338 Reference
Manual to set manually).
3.3. Synthesis Stages
Next-generation timing applications require a wide
range of frequencies that are often non-integer related.
Traditional clock architectures address this by using
multiple single PLL ICs, often at the expense of BOM
complexity and power. The Si5338 uses patented
MultiSynth technology to dramatically simplify timing
architectures by integrating the frequency synthesis
capability of four Phase-Locked Loops (PLLs) in a
single
device,
greatly
reducing
size
and
power
requirements versus traditional solutions.
÷P2
÷P1
IN3
IN2
IN1
IN6
IN4
IN5
Osc
P1DIV_IN
To
Sy
nt
he
si
s
S
ta
g
e
P2DIV_IN
noclk
IN2 / IN6
IN1 / IN5
100
50
0.1 uF
IN3 / IN4
50
Rs
IN2
IN1
XTAL
Osc
To synthesis stage
or output selectors
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9761ARSZ | IC DAC 10BIT DUAL 40MSPS 28-SSOP |
| VI-J0R-MZ-F2 | CONVERTER MOD DC/DC 7.5V 25W |
| SI5338K-A-GM | IC CLK GEN I2C BUS PROG 24QFN |
| D38999/20KF32PC | CONN RCPT 32POS WALL MNT W/PINS |
| MS3101A36-8S | CONN RCPT 47POS FREE HNG W/SCKT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5338N-A-GMR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C Program Clk Gen 0.16-710MHz 4Clk In RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5338N-B01504-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338N-B01504-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338N-B01552-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338N-B01552-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。