- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8973 > SI5338H-A-GM (Silicon Laboratories Inc)IC CLK GEN I2C BUS PROG 24QFN PDF資料下載
參數(shù)資料
| 型號： | SI5338H-A-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 37/44頁 |
| 文件大小： | 0K |
| 描述： | IC CLK GEN I2C BUS PROG 24QFN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 系列： | MultiSynth™ |
| 類型： | * |
| PLL： | 是 |
| 輸入： | CML，HCSL，HSCL，LVDS，LVPECL，晶體 |
| 輸出： | CMOS，HCSL. HSTL. LVDS. LVPECL. SSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 350MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN（4x4） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當(dāng)前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
Si5338
42
Rev. 1.3
DOCUMENT CHANGE LIST
Revision 0.2 to 0.3
Changed minimum output clock frequency from
5MHz to 1MHz.
Updated slew rates.
Updated " Features" on page 1.
Updated Table 6, “Input and Output Clock
Deleted Table 12, “Output Driver Slew Rate Control”.
Revision 0.3 to 0.5
Major editorial changes to all sections to improve
clarity
Completed electrical specification tables with final
characterization results
Revised the maximum input and output frequencies
from 700 MHz to 710 MHz
Improved jitter specifications to reflect updated
characterization results
Added new Si5338N/P/Q ordering codes
Added typical application diagrams
Added an application section to highlight the
flexibility of the Si5338 in various timing functions
Added a configuration section to clarify configuration
options
Revision 0.5 to 0.55
Editorial changes to section 3.5 “Configuring the
Si5338” to improve clarity on ordering custom
Si5338 and on configuring “blank” Si5338.
Added pin numbers to device package drawings.
Updated ordering information to include evaluation
boards.
Updated first page description and applications
Added
JC to specification tables.
Added GbE RM jitter specification with 1.875–
20 MHz integration band.
Revision 0.55 to 0.6
Changed output duty cycle to 45–55%.
All I2C address now in binary.
Changed ordering information to reflect 710 MHz
limit.
Info on POR and soft reset added.
Updated Figure 15 on page 27.
Added register section.
Update programming procedure in “3.5. Configuring
the Si5338” to improve robustness.
Updated Figure 9 to include the entire programming
procedure.
Detectors" on page 18 to show the location of the
LOS detector circuits.
Updated input circuit diagrams in "3.2. Input Stage"
Update block diagrams with new input circuit
diagrams.
Revision 0.6 to 0.65
page 22 for consistency with register description.
Revision 0.65 to 1.0
Expanded PCI jitter specifications in Table 12.
Moved “Si5338 Registers” section to AN411.
Revised CMOS output currents down for each
CMOS driver that is active in Table 3.
Clarified CMOS output loads in Table 3
Added peak reflow temperature and footnote in
Added sticky and mask register info in "3.6. Status
Added more information to Table note about CMOS
outputs and jitter in Table 12.
Changed all reference of MultiSynth Mn to MSn
Added "11. Top Marking" on page 40.
Reworded 3.5.2 and 3.5.3 for clarity.
Revision 1.0 to 1.1
Replaced all references to AN411 with "Si5338
Reference Manual" (AN411 has been replaced by
the Si5338 Reference Manual).
Clarified crystal specifications in Tables 8, 9, 10, 11
and added references to AN360.
Revision 1.1 to 1.2
Updated Table 2 on page 4.
Added CML current consumption specification.
Updated Table 6 on page 8.
Corrected tR/tF for output clocks (single-ended) from
1.7 ns (max ) to 2.0 ns (max).
Added CML Output Voltage parameter.
Updated Table 12 on page 13.
Updated typical specifications for total jitter for PCI
Express 1.1 Common clocked topology.
Updated typical specifications for RMS jitter for PCI
Express 2.1 Common clocked topology.
Removed RMS jitter specification for PCI Express 2.1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MS3454W14S-9S | CONN RCPT 2POS JAM NUT W/SCKT |
| SI5338E-A-GM | IC CLK GEN I2C BUS PROG 24QFN |
| JN1KS10PL2 | CONN RCPT 10POS W/O PIN WALL MT |
| MS27468E17A55S | CONN RCPT 55POS JAM NUT W/SCKT |
| VE-JTY-MZ-F1 | CONVERTER MOD DC/DC 3.3V 16.5W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5338H-A-GMR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C-Program Clk Gen 0.16-350MHz inc/dec RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5338H-B00191-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338H-B00300-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338H-B00300-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338H-B00385-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。