Si5338
6
Rev. 1.3
Table 5. Performance Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
PLL Acquisition Time
tACQ
——
25
ms
PLL Tracking Range
fTRACK
5000
20000
—
ppm
PLL Loop Bandwidth
fBW
—1.6
—
MHz
MultiSynth Frequency
Synthesis Resolution
fRES
Output frequency < Fvco/8
0
1
ppb
CLKIN Loss of Signal Detect
Time
tLOS
—2.6
5
s
CLKIN Loss of Signal Release
Time
tLOSRLS
0.01
0.2
1
s
PLL Loss of Lock Detect Time
tLOL
—5
10
ms
POR to Output Clock Valid
(Pre-programmed Devices)
tRDY
——
2
ms
Input-to-Output Propagation
Delay
tPROP
Buffer Mode
(PLL Bypass)
—2.5
4
ns
Output-Output Skew
tDSKEW
——
100
ps
POR to I2C Ready
——
15
ms
Programmable Initial
Phase Offset
POFFSET
–45
—
+45
ns
Phase Increment/Decrement
Accuracy
PSTEP
——
20
ps
Phase Increment/Decrement
Range
PRANGE
–45
—
+45
ns
MultiSynth range for phase
increment/decrement
fPRANGE
5—
MHz
Phase Increment/Decrement
Update Time
PUPDATE
MultiSynth output >18 MHz
667
—
ns
Notes:
2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept
between 5 MHz and Fvco/8.
3. Update rate via I2C is also limited by the time it takes to perform a write operation.
4. Default value is 0.5% down spread.
5. Default value is ~31.5 kHz.