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參數(shù)資料
| 型號(hào)： | SI5334C-A00135-GMR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, QCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件頁(yè)數(shù)： | 8/34頁(yè) |
| 文件大?。?/td> | 233K |
| 代理商： | SI5334C-A00135-GMR |
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Si5334
16
Preliminary Rev. 0.16
An OEB pin is provided to enable/disable the output
clocks. When OEB = 0, all outputs that have been
factory programmed will be on. When OEB = 1, all clock
outputs that have been factory programmed will be off
and held to a low level.
2.6. Output Clock Initial Phase Offset
Each CLKn output of the Si5334 can have its own
unique initial phase offset over a range of +- 45 ns with
an accuracy of 20 ps. When the respective R divider is
not set to 1, this function is not supported.
2.7. Output Clock Phase Increment and
Decrement
The Si5334D/E/F has a pin-controlled phase increment/
decrement feature that allows the user to adjust the
phase of 1 or more output clocks via pin control. Since
their is only 1 pin for increment and 1 pin for decrement,
each output clock channel needs to be enabled or
disabled for this feature. In addition, the magnitude of
the phase step must be set for each clock output
channel. The phase adjustment accuracy is 20 ps over
a range of ±45 ns, and the phase transition is glitchless.
This feature is not available on any clock output that has
Spread Spectrum enabled. The maximum clock output
frequency supported in this mode of operation is Fvco/
8, where Fvco is the frequency of the device's internal
voltage controlled oscillator for the configured frequency
plan. The phase can be changed at a maximum rate of
1.5 MHz. In order to increment or decrement phase it is
necessary to input a positive pulse of >100ns followed
by a low of >100 ns. Since this feature uses pins 3 and
4, the reference clock must be input at pins 1 and 2 or
the crystal used across these pins. Once a Si5334/D/E/
F
is
factory-programmed,
the
phase
increment/
decrement parameters cannot be changed. If one
desires to subsequently change the phase increment/
decrement parameters on a factory-programmed part,
the Si5338 clock generator must be used.
If a phase decrement causes a single MultiSynth clock
period to be less than 8/Fvco, all clock outputs may turn
off for up to 10 clock periods and then come back on
with the phase setting before the illegal decrement.
2.8. Output Clock Frequency Increment
and Decrement
The
Si5334G/H/J
has
a
pin-controlled
frequency
increment/decrement feature that allows the user to
adjust the frequency at the output of MultiSynth0 only.
MultiSynth0 can be connected to any or all of the four
output clock buffers with the muxes shown in the
" Functional Block Diagram" on page 2. If frequency
increment and decrement is required on the other clock
outputs the Si5338 should be used. The magnitude of a
single frequency step must be factory-programmed.
Spread Spectrum and frequency increment/decrement
cannot both be active on the same clock output. There
is a single pin to control the frequency increment and a
single pin to control the frequency decrement. The
frequency increment or decrement step size can be
factory-programmed from as low as 1 ppm of the initial
frequency to a maximum that keeps the output of the
MultiSynth within the limits of 5 MHz to Fvco/8. If a
frequency increment causes the MultiSynth0 output
frequency to go above Fvco/8, then all output clocks
may turn off for up to 10 clock cycles and then come
back on at the frequency before the increment. If the
output frequency needs to go below 5 MHz, refer to
"2.9. R Divider Considerations" on page 16 for further
information. The frequency transition is glitchless. The
frequency can be changed at a maximum rate of
1.5 MHz. In order to increment or decrement frequency
it is necessary to input a positive pulse of >100 ns
followed by a low of > 100 ns. Since this feature uses
pins 3 and 4, the reference clock must be input at pins 1
and 2 or the crystal used across these pins. Once a
Si5334/G/H/J is factory-programmed, the frequency
increment/decrement parameters cannot be changed. If
one desires to subsequently change the frequency
increment/decrement parameters on a programmed
part, the Si5338 clock generator must be used.
2.9. R Divider Considerations
When the requested output frequency of a channel is
below
5 MHz,
the
Rn
(n = 0,1,2,3)
divider
will
automatically be set and enabled. When the Rn divider
is active the step size range of the frequency increment
and decrement function will decrease by the Rn divide
ratio. The Rn divider can be set to {1, 2, 4, 8, 16, 32}.
Non-unity settings of R0 will affect the Finc/Fdec step
size at the MultiSynth0 output. For example, if the
MultiSynth0 output step size is 2.56 MHz and R0 = 8,
the step size at the output of R0 will be 2.56 MHz
divided by 8 = .32 MHz. When the Rn divider is set to
non-unity, the initial phase of the CLKn output with
respect to other CLKn outputs is not guaranteed.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5334C-A00136-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube |
| SI5334C-A00136-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5334C-A00137-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube |
| SI5334C-A00137-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5334C-A00138-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube |
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