
Si5334
Preliminary Rev. 0.16
21
17
CLK1B
O
Multi
Output Clock B for Channel 1
May be a single-ended output or half of a differential
output with CLK1A being the other differential half.
If unused, this pin must be tied to VDD pin 24. If unused
leave this pin floating.
18
CLK1A
O
Multi
Output Clock A for Channel 1
May be a single-ended output or half of a differential
output with CLK1B being the other differential half. If
unused leave this pin floating.
19
OEB
I
LVCMOS
Output Enable Low
When low, all the factory-programmed outputs are
enabled. When high all factory programmed outputs are
forced to a logic low.
20
VDDO0
VDD
Supply
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK0A,B.
A 0.1 F capacitor must be located very close to this pin.
If CLK0 is not used, this pin must be tied to VDD (pin 7,
24).
21
CLK0B
O
Multi
Output Clock B for Channel 0
May be a single-ended output or half of a differential
output with CLK0A being the other differential half. If
unused leave this pin floating.
22
CLK0A
O
Multi
Output Clock A for Channel 0
May be a single-ended output or half of a differential
output with CLK0B being the other differential half. If
unused leave this pin floating.
23
RSVD_GND
GND
Ground.
Must be connected to system ground.
24
VDD
Supply
Core Supply Voltage.
The device operates from a 1.8, 2.5, or 3.3 V supply. A
0.1 F bypass capacitor should be located very close to
this pin.
GND
PAD
GND
Ground Pad.
This is the large pad in the center of the package.
Device specifications cannot be guaranteed unless the
ground pad is properly connected to a ground plane on
the PCB. See section 6.0 for the PCB pad sizes and
ground via requirements.
Table 15. Si5334 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Type
Description