參數(shù)資料
型號(hào): SI5319B-C-GM
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 35/50頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK MULT/ATTENUATOR 36QFN
標(biāo)準(zhǔn)包裝: 490
系列: DSPLL®
類型: 時(shí)鐘/頻率倍增器,抖動(dòng)衰減器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH
輸入: 時(shí)鐘,晶體
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 808MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤
Si5319
40
Rev. 1.0
5. Pin Descriptions: Si5319
Pin #
Pin Name
I/O
Signal Level
Description
1
RST
ILVCMOS
External Reset.
Active low input that performs external hardware reset of device.
Resets all internal logic to a known state and forces the device regis-
ters to their default value. Clock outputs are disabled during reset. The
part must be programmed after a reset or power-on to get a clock out-
put. See Family Reference Manual for details.
This pin has a weak pull-up.
2, 4, 9,
12–14,
30,
33–35
NC
No Connection.
Leave floating. Make no external connections to this pin for normal
operation.
3INT_CB
O
LVCMOS
Interrupt/CKIN Invalid Indicator.
This pin functions as a device interrupt output or an alarm output for
CKIN. If used as an interrupt output, INT_PIN must be set to 1. The pin
functions as a maskable interrupt output with active polarity controlled
by the INT_POL register bit.
If used as an alarm output, the pin functions as a LOS alarm indicator
for CKIN. Set CK_BAD_PIN = 1 and INT_PIN =0.
0 = CKIN present.
1 = LOS on CKIN.
The active polarity is controlled by CK_BAD_POL. If no function is
selected, the pin tristates.
5, 10,
32
VDD
Supply
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capaci-
tors should be associated with the following VDD pins:
50.1 F
10
0.1 F
32
0.1 F
A 1.0 F should also be placed as close to the device as is practical.
Note:
Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).
1
2
3
29
30
31
32
33
34
35
36
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
NC
RST
NC
INT_CB
GND
VDD
XA
VDD
RA
TE0
NC
RA
TE1
CKI
N
1+
CKI
N
1–
CS
SCL
SDA_SDO
A1
A2_SS
SDI
CKO
U
T
NC
GND
VD
D
NC
CMODE
GND
Pad
A0
GND
9
18
19
28
XB
LO
L
GND
CKO
U
T
+
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