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參數(shù)資料
| 型號(hào)： | SI5317A-C-GMR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 711 MHz, OTHER CLOCK GENERATOR, QCC36 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36 |
| 文件頁數(shù)： | 1/46頁 |
| 文件大?。?/td> | 407K |
| 代理商： | SI5317A-C-GMR |
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Rev. 1.1 4/11
Copyright 2011 by Silicon Laboratories
Si5317
P IN-C ONTROLLED 1–711 MH Z J ITTER C LEANING C LOCK
Features
Applications
Description
The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications
that require jitter attenuation without clock multiplication. The Si5317 accepts a
single clock input ranging from 1 to 711 MHz and generates two low jitter clock
outputs at the same frequency. The clock frequency range and loop bandwidth are
selectable from a simple look-up table. The Si5317 is based on Silicon
Laboratories' 3rd-generation DSPLL technology, which provides jitter attenuation
on any frequency in a highly integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The DSPLL loop bandwidth is user
selectable, providing jitter performance optimization at the application level.
Functional Block Diagram
Provides jitter attenuation for any clock
frequency
One clock input / two clock outputs
Input/output frequency range:
1–711 MHz
Ultra low jitter: 300 fs
(12 kHz–20 MHz) typical
Simple pin control interface
Selectable loop bandwidth for jitter
attenuation: 60 Hz–8.4 kHz
Meets OC-192 GR-253-CORE jitter
specifications
Selectable output clock signal
format: LVPECL, LVDS, CML or
CMOS
Single supply: 1.8, 2.5, or 3.3 V
Loss of lock and loss of signal
alarms
VCO freeze during LOS/LOL
On-chip voltage regulator with high
PSRR
Small size: 6 x 6 mm, 36-QFN
Wide temperature range: –40 to
+85 C
Data converter clocking
Wireless infrastructure
Networking, SONET/SDH
Switches and routers
Medical instrumentation
Test and measurement
DSPLL
Clock In
Clock Out1
Signal Format [1:0]
Status/Control
Loss of Lock
Loss of Signal
Bandwidth Select [1:0]
XTAL/Clock Rate [1:0]
Frequency Table
High
PSRR
Regulator
Frequency Select [3:0]
Clock Out2
XTAL/Clock
Phase Skew INC/DEC
VDD (1.8, 2.5, 3.3 V)
GND
Ordering Information:
See page 40.
Pin Assignments
1
2
3
29
30
31
32
33
34
35
36
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
FRQTBL
NC
RST
NC
LOS
GND
VDD
XA
VD
D
RA
T
E
0
NC
DB
L2_BY
RA
T
E
1
CK
IN+
CKI
N
–
NC
BWSEL0
BWSEL1
FRQSEL1
FRQSEL2
FRQSEL3
CK
O
U
T
1
–
SFOU
T1
GND
VD
D
SF
O
U
T
0
CKOU
T
2
-
CKOU
T
2
+
NC
GND
Pad
FRQSEL0
INC
9
18
19
28
XB
LOL
DEC
CKO
U
T
1
+
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Si5317B-C-GM | 功能描述:標(biāo)準(zhǔn)時(shí)鐘振蕩器 Pin-Program. Jitter Cleaning Clock RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負(fù)載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列: |
| SI5317B-C-GMR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Pin-Program Jitter Clean Clk 1In/2Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| Si5317C-C-GM | 功能描述:標(biāo)準(zhǔn)時(shí)鐘振蕩器 Pin-Program. Jitter Cleaning Clock RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負(fù)載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列: |
| SI5317C-C-GMR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Pin-Program Jitter Clean Clk 1In/2Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| Si5317D-C-GM | 功能描述:標(biāo)準(zhǔn)時(shí)鐘振蕩器 Pin-Program. Jitter Cleaning Clock RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負(fù)載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列: |
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