參數(shù)資料
型號: SI51219-A01AFT
廠商: Silicon Laboratories Inc
文件頁數(shù): 1/12頁
文件大?。?/td> 0K
描述: IC CLK GEN FACTORY CONFIG 8TSSOP
標(biāo)準(zhǔn)包裝: 100
類型: *
PLL: 帶旁路
輸入: 時鐘,晶體
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 無/無
頻率 - 最大: 200MHz
除法器/乘法器: 是/無
電源電壓: 2.375 V ~ 3.63 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 8-TSSOP
包裝: 管件
Preliminary Rev. 0.7 1/12
Copyright 2012 by Silicon Laboratories
Si51219
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si51219
T HREE O UTPUTS F ACTORY P ROGRAMMABLE C LOCK
G ENERATOR
Features
Applications
Description
The factory programmable Si51219 is a low power, small footprint and
frequency flexible programmable clock generator targeting low power, low
cost and high volume consumer and embedded applications. The device
operates from a single crystal or an external clock source and generates
1 to 3 outputs up to 200 MHz. They are factory programmed to provide
customized output frequencies, control inputs and ac parameter tuning
like output drive strength that are optimized for customer board condition
and application requirements. A separate VDDO supply pin supports
clock output at a different voltage level.
Functional Block Diagram
Generates up to 3 CMOS clock
outputs from 3 to 200 MHz
Accepts crystal or reference
clock input
3 to 166 MHz reference clock input
8 to 48 MHz crystal input
Programmable FSEL, SSEL,
SSON, PD, and OE input
functions
Low power dissipation
Separate voltage supply pins
VDD = 2.5 to 3.3 V
VDDO= 1.8 to 3.3 V (VDDO VDD)
0.25% to 1.0% Spread Spectrum
(Center Spread)
Low cycle-cycle jitter
Programmable output rise and
fall times
8-pin TSSOP package
Crystal/XO replacement
EMI reduction
Portable devices
Digital still camera
IP phone
Home gateway
2
3
1
5
4
6
To Pin 4 and Pin 6
To Core
Programmable
Configuration
Register
PLL with
Modulation
Control
Buffers,
Dividers,
and
Switch
Matrix
SSCLK1/
REFCLK/
0E2/FSEL/
SSEL/SS0N
SSCLK2/
REFCLK_D
0E1/FSEL/
SSEL/SS0N/PD
XIN/
CLKIN
XOUT
VDD
VSS
V-REG
8
VDD0
To Pin 7
7 SSCLK3 (VDD0)
Patents pending
Ordering Information:
Pin Assignments
8
Si51219
7
6
5
4
1
2
3
VDDO
SSCLK3
SSCLK2/REFCLK_D
FSEL/SSEL/SSON/
PD/OE1
VSS
SSCLK1/REFCLK
FSEL/SSEL/SSON/
OE2
XIN/CLKIN
XOUT
VDD
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