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參數(shù)資料
| 型號： | Si4123G |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR GSM AND GPRS WIRELESS COMMUNICATIONS |
| 中文描述： | 雙波段射頻合成器集成的GSM和GPRS無線通訊和VCO |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 466K |
| 代理商： | SI4123G |
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Si4133G
Rev. 1.1
15
Functional Description
The Si4133G is a monolithic integrated circuit that
performs IF and dual-band RF synthesis for many
wireless applications such as GSM, DCS1800, and
PCS1900. Its fast transient response also makes the
Si4133G especially well suited to GPRS and HSCSD
multislot applications where channel switching and
settling times are critical. This integrated circuit (IC),
with a minimum number of external components, is all
that is necessary to implement the frequency synthesis
function.
The Si4133G has three complete phase-locked loops
(PLLs) with integrated voltage-controlled oscillators
(VCOs). The low phase noise of the VCOs makes the
Si4133G suitable for use in demanding wireless
communications applications. Also integrated are phase
detectors, loop filters, and reference dividers. The IC is
programmed through a three-wire serial interface.
One PLL is provided for IF synthesis, and two PLLs are
provided for dual-band RF synthesis. One RF VCO is
optimized to have its center frequency set between
947 MHz and 1720 MHz, while the second RF VCO is
optimized to have its center frequency set between
789 MHz and 1429 MHz. The IF VCO is optimized to
have its center frequency set between 526 MHz and
952 MHz. Each PLL can adjust its output frequency by
±5% relative to its VCO center frequency.
The center frequency of each of the three VCOs is set
by connection of an external inductance. Inaccuracies in
the value of the inductance are compensated for by the
Si4133G’s proprietary self-tuning algorithm. This
algorithm is initiated each time the PLL is powered-up
(by either the PWDNB pin or by software) and/or each
time a new output frequency is programmed.
The two RF PLLs share a common output pin, so only
one PLL is active at a given time. Because the two
VCOs can be set to have widely separated center
frequencies, the RF output can be programmed to
service different frequency bands, thus making the
Si4133G ideal for use in dual-band cellular handsets.
The unique PLL architecture used in the Si4133G
produces a transient response that is superior in speed
to fractional-N architectures without suffering the high
phase noise or spurious modulation effects often
associated with those designs.
Serial Interface
A timing diagram for the serial interface is shown in
Figure 2 on page 7. Figure 3 on page 7 shows the
format of the serial word.
The Si4133G is programmed serially with 22-bit words
comprised of 18-bit data fields and 4-bit address fields.
When the serial interface is enabled (i.e., when SENB is
low) data and address bits on the SDATA pin are
clocked into an internal shift register on the rising edge
of SCLK. Data in the shift register is then transferred on
the rising edge of SENB into the internal data register
addressed in the address field. The serial interface is
disabled when SENB is high.
Table 10 on page 20 summarizes the data register
functions and addresses. The internal shift register will
ignore any leading bits before the 22 required bits.
Setting the VCO Center Frequencies
The PLLs can adjust the IF and RF output frequencies
±5% with respect to their VCO center frequencies. Each
center frequency is established by the value of an
external inductance connected to the respective VCO.
Manufacturing tolerances of ±10% for the external
inductances are acceptable. The Si4133G will
compensate for inaccuracies in each inductance by
executing a self-tuning algorithm following PLL power-
up or following a change in the programmed output
frequency.
Because the total tank inductance is in the low nH
range, the inductance of the package needs to be
considered in determining the correct external
inductance. The total inductance (L
TOT
) presented to
each VCO is the sum of the external inductance (L
EXT
)
and the package inductance (L
PKG
). Each VCO has a
nominal capacitance (C
NOM
) in parallel with the total
inductance, and the center frequency is as follows:
or
Tables 6 and 7 summarize these characteristics for
each VCO.
f
CEN
2
π
L
TOT
C
NOM
---------------------------------------------
=
f
CEN
L
EXT
2
π
L
PKG
+
(
)
C
NOM
----------------------------------------------------------------------
=
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI4123G-BM | 制造商:Silicon Laboratories Inc 功能描述: |
| SI4123G-BMR | 功能描述:鎖相環(huán) - PLL CONTACT SILICON LABS FOR AVAILABILITY RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| SI4123G-BT | 制造商:SILABS 制造商全稱:SILABS 功能描述:DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR GSM AND GPRS WIRELESS COMMUNICATIONS |
| SI4123GM-EVB | 制造商:Silicon Laboratories Inc 功能描述: |
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