參數(shù)資料
型號: SI4123-D-GT
廠商: Silicon Laboratories Inc
文件頁數(shù): 15/36頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER RF1/IF 24TSSOP
標(biāo)準(zhǔn)包裝: 62
類型: 頻率合成器
PLL:
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 1.8GHz
除法器/乘法器: 是/無
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
其它名稱: 336-1175
Si4133
22
Rev. 1.61
Register 0. Main Configuration
Address Field = A[3:0] = 0000
Bit
D17 D16 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
0
AUXSEL
[1:0]
IFDIV
[1:0]
0000
LPWR
0
AUTO
PDB
AUTO
KP
RF
PWR
0
Bit
Name
Function
17:14
Reserved
Program to zero.
13:12
AUXSEL[1:0]
Auxiliary Output Pin Definition.
00 = Reserved.
01 = Force output low.
10 = Reserved.
11 = Lock Detect—LDETB.
11:10
IFDIV[1:0]
IF Output Divider.
00 = IFOUT = IFVCO Frequency
01 = IFOUT = IFVCO Frequency/2
10 = IFOUT = IFVCO Frequency/4
11 = IFOUT = IFVCO Frequency/8
9:6
Reserved
Program to zero.
5
LPWR
Output Power-Level Settings for IF Synthesizer Circuit.
0 = RLOAD 500 —normal power mode.
1 = RLOAD 500 —low power mode.
4
Reserved
Program to zero.
3
AUTOPDB
Auto Powerdown.
0 = Software powerdown is controlled by Register 2.
1 = Equivalent to setting all bits in Register 2 = 1.
2AUTOKP
Auto KP Setting.
0 = KPs are controlled by Register 1.
1 = KPs are set according to Table 9 on page 18.
1
RFPWR
Program to zero. (Used for extended frequency operation. See AN41 for
more information.)
0
Reserved
Program to zero.
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參數(shù)描述
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