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參數(shù)資料
| 型號： | SI3216MDCX-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 51/122頁 |
| 文件大?。?/td> | 0K |
| 描述： | DAUGHTER CARD W/DISCRETE INTRFC |
| 標準包裝： | 1 |
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Si3216
34
Rev. 1.0
Not
Recommended
fo
r N
ew
D
esi
gn
s
power supply (number of REN supported).
For this solution, an n-channel power MOSFET (M1)
switches the current flow through a power transformer
T1. T1 is specified in “AN45: Design Guide for the
Si3210/15/16 DC-DC Converter” and includes several
taps on the primary side to facilitate a wide range of
input voltages. The “M” version of the ProSLIC must be
used for the application circuit depicted in Figure 14 on
page 24 because the DCFF pin is used to drive M1
directly and, therefore, must be the same polarity as
DCDRV. DCDRV is not used in this circuit option;
connecting
DCFF
and
DCDRV
together
is
not
recommended.
2.2.4. DC-DC Converter Architecture
The control logic for a pulse-width modulated (PWM)
dc-dc converter is incorporated in the ProSLIC. Output
pins DCDRV and DCFF are used to switch a bipolar
transistor or MOSFET. The polarity of DCFF is opposite
that of DCDRV.
The dc-dc converter circuit is powered on when the
DCOF bit in the powerdown register (direct Register 14,
bit 4) is cleared to 0. The switching regulator circuit
within the ProSLIC is a high-performance, pulse-width
modulation controller. The control pins are driven by the
PWM controller logic in the ProSLIC. The regulated
output voltage (VBAT) is sensed by the SVBAT pin and
used to detect whether the output voltage is above or
below an internal reference for the desired battery
voltage. The dc monitor pins SDCH and SDCL monitor
input current and voltage to the dc-dc converter external
circuitry. If an overload condition is detected, the PWM
controller will turn off the switching transistor for the
remainder of a PWM period to prevent damage to
external components. It is important that the proper
value of R18 be selected to ensure safe operation.
Guidance is given in “AN45: Design Guide for the
Si3210/15/16 DC-DC Converter”.
The PWM controller operates at a frequency set by the
dc-dc Converter PWM register (direct Register 92).
During a PWM period the outputs of the control pins
DCDRV and DCFF are asserted for a time given by the
read-only
PWM
Pulse
Width
register
(direct
Register 94).
The dc-dc converter must be off for some time in each
cycle to allow the inductor or transformer to transfer its
stored energy to the output capacitor, C9. This minimum
off time can be set through the dc-dc Converter
Switching Delay register, (direct Register 93). The
number of 16.384 MHz clock cycles that the controller is
off is equal to DCTOF (bits 0 through 4) plus 4. If the dc
monitor pins detect an overload condition, the dc-dc
converter interrupts its conversion cycles regardless of
the register settings to prevent component damage.
These inputs should be calibrated by writing the DCCAL
bit (bit 7) of the dc-dc Converter Switching Delay
register, direct Register 93, after the dc-dc converter
has been turned on.
Because the ProSLIC dynamically regulates its own
battery supply voltage using the dc-dc converter
controller, the battery voltage (VBAT) is offset from the
negative-most terminal by a programmable voltage
(VOV) to allow voltage headroom for carrying audio
signals.
As mentioned previously, the ProSLIC dynamically
adjusts VBAT to suit the particular circuit requirement. To
illustrate this, the behavior of VBAT in the Active state is
shown in Figure 19. In the Active state, the TIP-to-RING
open circuit voltage is kept at VOC in the constant
voltage region while the regulator output voltage,
VBAT =VCM + VOC + VOV.
When the loop current attempts to exceed ILIM, the dc
line driver circuit enters constant current mode allowing
the TIP to RING voltage to track RLOOP. As the TIP
terminal is kept at a constant voltage, it is the RING
terminal voltage that tracks RLOOP and, as a result, the
|VBAT| voltage will also track RLOOP. In this state,
|VBAT|= ILIM x RLOOP + VCM + VOV. As RLOOP
decreases below the VOC/ILIM mark, the regulator
output
voltage
can
continue
to
track
RLOOP
(TRACK = 1), or the RLOOP tracking mechanism is
stopped
when
|VBAT|=|VBATL| (TRACK = 0). The
former case is the more common application and
provides the maximum power dissipation savings. In
principle, the regulator output voltage can go as low as
|VBAT|= VCM+ VOV, offering significant power savings.
When TRACK = 0, |VBAT| does not decrease below
VBATL. The RING terminal voltage, however, continues
to decrease with decreasing RLOOP. The power
dissipation on the NPN bipolar transistor driving the
RING terminal can become large and may require a
higher power rating device. The non-tracking mode of
operation is required by specific terminal equipment
which, in order to initiate certain data transmission
modes, goes briefly on-hook to measure the line voltage
to determine whether there is any other off-hook
terminal equipment on the same line. TRACK = 0 mode
is desired since the regulator output voltage has long
settling time constants (tens of milliseconds) and cannot
change rapidly for TRACK = 1 mode. Therefore, the
brief
on-hook
voltage
measurement
would
yield
approximately the same voltage as the off-hook line
voltage and would cause the terminal equipment to
incorrectly sense another off-hook terminal.
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