Idle Channel Noise6
參數(shù)資料
型號： SI3202-G-GS
廠商： Silicon Laboratories Inc
文件頁數(shù)： 17/112頁
文件大?。?/td> 0K
描述： IC LINEFEED INTRFC 125V 16SOIC
標準包裝： 48
功能： 用戶線路接口概念（SLIC），CODEC
接口： GCI，PCM，SPI
電路數(shù)： 2
電源電壓： 3.13 V ~ 5.25 V
電流 - 電源： 65mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm Width）裸露焊盤
供應商設備封裝： 16-SOIC N
包裝： 管件
包括： 電池切換，BORSCHT 功能，DTMF 生成和解碼，F(xiàn)SK 音調生成，調制解調器和傳真音調檢測
Si3220/25 Si3200/02
12
Rev. 1.3
Not
Recommended
fo
r N
ew
D
esi
gn
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Noise Performance
Idle Channel Noise6
C-Message weighted
—
12
15
dBrnC
Psophometric weighted
—
–78
–75
dBmP
3 kHz flat
—
18
dBrn
PSRR from VDD1 – VDD4
RX and TX, dc to 3.4 kHz
40
—
dB
PSRR from VBAT
RX and TX, dc to 3.4 kHz
60
—
dB
Longitudinal Performance
Longitudinal to Metallic/PCM
Balance (forward or reverse)
200Hz to 1kHz
58
70
—
dB
1kHz to 3.4kHz
53
58
—
dB
Metallic/PCM to Longitudinal
Balance
200 Hz to 3.4 kHz
40
—
dB
Longitudinal Impedance7
200 Hz to 3.4 kHz at TIP or RING
Register-dependent
OBIAS/ABIAS
00 = 4 mA
01 = 8 mA
10 = 12 mA
11 = 16 mA
—
50
25
20
—
Longitudinal Current per Pin7
Active off-hook
200Hz to 3.4kHz
Register-dependent
OBIAS/ABIAS
00 = 4 mA
01 = 8 mA
10 = 12 mA
11 = 16 mA
—
4
8
10
—
mA
Table 5. AC Characteristics (Continued)
(VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Test Condition
Min
Typ
Max
Unit
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the /A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. The digital gain block is a linear multiplier that is programmable from –
to +6 dB. The step size in dB varies over the
complete range. See "3.25. Audio Path Processing" on page 70.
5. VDD1 – VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors, RL = 600 , ZS = 600 synthesized using RS register
coefficients.
6. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and off-
hook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the
sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application.
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