參數(shù)資料
型號: SI3056SSI1-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 5/94頁
文件大?。?/td> 0K
描述: BOARD EVAL SI3056/SI3019 SSI
標準包裝: 1
主要目的: 電信,數(shù)據(jù)采集裝置(DAA)
已用 IC / 零件: Si3056
已供物品: 板,CD
Si3056
Si3018/19/10
Rev. 1.05
13
Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = 1)
Table 9. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 1)
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL =20pF)
Parameter1, 2
Symbol
Min
Typ
Max
Unit
Cycle Time, SCLK
tc
244
1/256 Fs
ns
SCLK Duty Cycle
tdty
—50
%
Delay Time, SCLK
↑ to FSYNC↑
td1
——
20
ns
Delay Time, SCLK
↑ to FSYNC↓
td2
——
20
ns
Delay Time, SCLK
↑ to SDO Valid
td3
——
20
ns
Delay Time, SCLK
↑ to SDO Hi-Z
td4
——
20
ns
Delay Time, SCLK
↑ to FSD↓
td5
——
20
ns
Setup Time, SDO Before SCLK
tsu
25
ns
Hold Time, SDO After SCLK
th
20
ns
Notes:
1.
All timing is referenced to the 50% level of the waveform. Input test levels are VIH =VD – 0.4 V, VIL =0.4 V.
2.
D15
D1
D0
SCLK
FSYNC
(mode 1)
SDO
(master)
FSD
SDI
t
c
SDO
(slave 1)
t
d1
D14
t
d2
t
d3
D15
D14
D13
D0
t
su
t
h
t
d4
t
d3
D15
t
d5
t
h
t
su
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