參數(shù)資料
型號(hào)： SI3056PPT2-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 2/94頁
文件大小： 0K
描述： BOARD EVAL FOR DAA SI3056/SI3010
標(biāo)準(zhǔn)包裝： 1
主要目的： 電信，數(shù)據(jù)采集裝置（DAA）
已用 IC / 零件： Si3056
已供物品： 板，CD
Si3056
Si3018/19/10
10
Rev. 1.05
Figure 2. General Inputs Timing Diagram
Table 5. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
DC Supply Voltage
VD
–0.5 to 3.6
V
Input Current, Si3056 Digital Input Pins
IIN
±10
mA
Digital Input Voltage
VIND
–0.3 to (VD + 0.3)
V
Operating Temperature Range
TA
–40 to 100
°C
Storage Temperature Range
TSTG
–65 to 150
°C
Note: Permanent device damage can occur if the above absolute maximum ratings are exceeded. Restrict functional
operation to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods might affect device reliability.
Table 6. Switching Characteristics—General Inputs
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
Parameter1
Symbol
Min
Typ
Max
Unit
Cycle Time, MCLK
tmc
16.67
—
1000
ns
MCLK Duty Cycle
tdty
40
50
60
%
MCLK Jitter Tolerance
tjitter
——
±2
ns
Rise Time, MCLK
tr
——
5
ns
Fall Time, MCLK
tf
——
5
ns
MCLK Before RESET
↑
tmr
10
—
cycles
RESET Pulse Width2
trl
250
—
ns
M0, M Before RESET
↑3
tmxr
20
—
ns
Notes:
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH = VD – 0.4 V, VIL = 0.4 V. Rise and fall times are referenced to the 20% and 80% levels of the waveform.
2. The minimum RESET pulse width is the greater of 250 ns or 10 MCLK cycle times.
3. M0 and M are typically connected to VD or GND and should not be changed during normal operation.
MCLK
M0, M1
t
r
RESET
t
mc
t
mr
t
f
t
mxr
V
IH
V
IL
t
rl
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