參數(shù)資料
型號： SI3056DC3-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 54/94頁
文件大?。?/td> 0K
描述： DAUGHTERCARD DAA SI3056/SI3008
標(biāo)準(zhǔn)包裝： 1
主要目的： 電信，數(shù)據(jù)采集裝置（DAA）
已用 IC / 零件： Si3056
已供物品： 板，CD
Si3056
Si3018/19/10
58
Rev. 1.05
Reset settings = 0000_0000 (serial mode 0,1)
Reset settings = 0011_1101 (serial mode 2)
Register 14. Serial Interface Control
Bit
D7
D6D5D4D3D2D1D0
Name
NSLV[2:0]
SSEL[1:0]
FSD
RPOL
DCE
Type
R/W
Bit
Name
Function
7:5
NSLV[2:0] Number of Slaves devices.
000 = 0 slaves. Redefines the FC/RGDT and RGDT/FSD pins.
001 = 1 slave device
010 = 2 slave devices
011 = 3 slave devices
100 = 4 slave devices (For four or more slave devices, the FSD bit MUST be set.)
101 = 5 slave devices
110 = 6 slave devices
111 = 7 slave devices
4:3
SSEL[1:0] Slave device select.
00 = 16-bit SDO receive data
01 = Reserved
10 = 15-bit SDO receive data, LSB = 1
11 = 15-bit SDO receive data, LSB = 0
2FSD
Delayed Frame Sync Control.
0 = Sets the number of SCLK periods between frame syncs to 32.
1 = Sets the number of SCLK periods between frame syncs to 16. This bit MUST be set when
Si3056 devices are slaves. For the master Si3056, only serial mode 1 is allowed when this bit
is set.
1RPOL
Ring Detect Polarity.
0=The FC/RGDT pin (operating as ring detect) is active low.
1=The FC/RGDT pin (operating as ring detect) is active high.
0DCE
Daisy-Chain Enable.
0 = Daisy-chaining disabled.
1 = Enables the Si3056 to operate with slave devices on the same serial bus. The FC/RGDT
signal (pin 7) becomes the ring detect output and the RDGT/FSD signal (pin 15) becomes the
delayed frame sync signal. ALL other bits in this register are ignored if DCE = 0.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
Si3056DC-EVB 功能描述:子卡和OEM板 Global DAA Daughter Card Only RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
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SI3056-D-ZS3R 制造商:Silicon Laboratories Inc 功能描述:MODEM CHIP CHIPSET 56KBPS - Tape and Reel
SI3056-F-FS 制造商:Silicon Laboratories Inc 功能描述:
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