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參數(shù)資料
| 型號(hào)： | SI3025-KS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT |
| 中文描述： | 3.3伏催化裂化/ JATE直接訪問安排 |
| 文件頁數(shù)： | 38/54頁 |
| 文件大小： | 1407K |
| 代理商： | SI3025-KS |
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Si3035
38
Rev. 1.2
Reset settings = 0111_0000
Reset settings = 0000_0000 (serial mode 0, 1, 2)
Register 6. DAA Control 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
CPE
ATM1 ARM1
PDL
PDN
ATM0 ARM0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Function
7
CPE
Charge Pump Enable.
0 = Charge pump is disabled.
1 = Charge pump is enabled. (The V
A
pin should not be connected to a supply.
V
D
= 3.3 V ± 10%.)
AOUT Transmit Path Level Control.
00 = –20 dB transmit path attenuation for call progress AOUT pin only.
01 = –32 dB transmit path attenuation for call progress AOUT pin only.
10 = Mutes transmit path for call progress AOUT pin only.
11 = –26 dB transmit path attenuation for call progress AOUT pin only.
6,1
ATM[1:0]
5,0
ARM[1:0]
AOUT Receive Path Level Control.
00 = 0 dB receive path attenuation for call progress AOUT pin only.
01 = –12 dB receive path attenuation for call progress AOUT pin only.
10 = Mutes receive path for call progress AOUT pin only.
11 = –6 dB receive path attenuation for call progress AOUT pin only.
4
PDL
Power Down Line-Side Chip.
0 = Normal operation. Program the clock generator before clearing this bit.
1 = Places the Si3012 in power down or reset state.
3
PDN
Power Down.
0 = Normal operation.
1 = Powers down the Si3021. A pulse on RESET is required to restore normal operation.
2
Reserved Read returns zero.
Register 7. PLL1 Divide N1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
N1[7:0]
Type
R/W
Bit
Name
Function
7:0
N1[7:0]
N1 Divider.
Contains the (value – 1) for determining the output frequency on PLL1.
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