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參數(shù)資料
| 型號： | SG556BYB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Mobile PentiumR Processor Application Clock Generator |
| 中文描述： | 99.8 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 62K |
| 代理商： | SG556BYB |
SG556
Mobile Pentium Processor Application Clock Generator
with SSCG, USB and Power Management Support
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07016 Rev. **
5/17/2001
Page 1 of 10
APPROVED PRODUCT
Product Features
Supports clock requirements for Mobile Pentium
Processor
2 Host and 5 PCI clocks
Separate supply pins for mixed (3.3/2.5V) voltage
application.
<175ps skew among CPU clocks.
< 250ps skew among PCI clocks.
48mhz for USB.
28-pin SSOP package for minimum board space.
Power management capabilities
Block Diagram
Frequency Table
SEL100/66#
0
1
*Down Spread 1.25% (total); **Down Spread .5% (total)
CPU
PCI
66.4 Mhz*
99.8 Mhz**
33.3 Mhz
33.2 MHz
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
VDDR
REF
VDDC
CPU0
CPU1
VSS
VDD
VSS
PCI_STOP#
CPU_STOP#
PWR_DWN#
48M
SEL100/66#
XIN
XOUT
VSS
PCI_F
PCI1
VDDP
PCI2
PCI3
VDDP
PCI4
PCI5
VSS
VDD
VSS
OSC
SEL1066#
PWR_DWN#
PCI_STOP#
VDDR
REF
VDDC
CPUCLK (0:1)
VDDP
48 MHz
PCI_F
PCI (1:5)
CPU_STOP#
PLL
PLL
XIN
XOUT
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