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參數(shù)資料
| 型號(hào)： | SG3524 |
| 廠商： | Microsemi Corporation |
| 英文描述： | REGULATING PULSE WIDTH MODULATOR |
| 中文描述： | 調(diào)控脈寬調(diào)制器 |
| 文件頁(yè)數(shù)： | 4/5頁(yè) |
| 文件大?。?/td> | 125K |
| 代理商： | SG3524 |
Philips Semiconductors
Product specification
SG3524
SMPS control circuit
1994 Aug 31
4
TIMING CAPACITOR VALUE (C–)–(
μ
F)
10
5
3
2
1.0
0.5
0.3
.001 .002
.005
.01 .02
.05
1
O
SL00178
Figure 5. Output Stage Dead Time as a Function of the Timing
Capacitor Value
T
T
100
50
20
10
5
2
1
100
50
20
10
5
200 5001ms2ms
OSCILLATOR PERIOD (
μ
s)
SL00179
Figure 6. Oscillator Period
as a Function of R
T
and C
T
FREQUENCY - (Hz)
V
80
60
40
20
0
10
100
1k
10k
100k
1M
10M
R
L
= RESISTANCE FROM
PIN 9 TO GND
R
L
= 30k
R
L
= 100k
R
L
= 1M
R
L
= 300k
R
L
= 30M
SL00180
Figure 7. Amplifiers Open-Loop Gain as a Function of
Frequency and Loading on Pin 9
Oscillator
The oscillator in the SG3524 uses an external resistor (R
T
) to
establish a constant charging current into an external capacitor (C
T
).
While this uses more current than a series-connected RC, it
provides a linear ramp voltage on the capacitor which is also used
as a reference for the comparator. The charging current is equal to
3.6 V
÷
R
T
and should be kept within the approximate range of 30
μ
A
to 2mA; i.e., 1.8k<R
T
<100k.
The range of values for C
T
also has limits as the discharge time of
C
T
determines the pulse-width of the oscillator output pulse. This
pulse is used (among other things) as a blanking pulse to both
outputs to insure that there is no possibility of having both outputs
on simultaneously during transitions. This output dead time
relationship is shown in Figure 5. A pulse width below approximately
0.5
μ
s may allow false triggering of one output by removing the
blanking pulse prior to the flip-flop’s reaching a stable state. If small
values of C
T
must be used, the pulse-width may still be expanded
by adding a shunt capacitance (
100pF) to ground at the oscillator
output. [(Note: Although the oscillator output is a convenient
oscilloscope sync input, the cable and input capacitance may
increase the blanking pulse-width slightly.)] Obviously, the upper
limit to the pulse width is determined by the maximum duty cycle
acceptable. Practical values of C
T
fall between 0.001 and 0.1
μ
F.
The oscillator period is approximately t=R
T
C
T
where t is in
microseconds when R
T
=
and C
T
=
μ
F. The use of Figure 6 will allow
selection of R
T
and C
T
for a wide range of operating frequencies.
Note that for series regulator applications, the two outputs can be
connected in parallel for an effective 0-90% duty cycle and the
frequency of the oscillator is the frequency of the output. For
push-pull applications, the outputs are separated and the flip-flop
divides the frequency such that each output’s duty cycle is 0-45%
and the overall frequency is one-half that of the oscillator.
External Synchronization
If it is desired to synchronize the SG3524 to an external clock, a
pulse of
+3V may be applied to the oscillator output terminal with
R
T
C
T
set slightly greater than the clock period. The same
considerations of pulse-width apply. The impedance to ground at
this point is approximately 2k
.
If two or more SG3524s must be synchronized together, one must
be designated as master with its R
T
C
T
set for the correct period.
The slaves should each have an R
T
C
T
set for approximately 10%
longer period than the master with the added requirement that
C
T
(slave)=one-half C
T
(master). Then connecting Pin 3 on all units
together will insure that the master output pulse—which occurs first
and has a wider pulse width—will reset the slave units.
Error Amplifier
This circuit is a simple differential input transconductance amplifier.
The output is the compensation terminal, Pin 9, which is a
high-impedance node (R
L
5M
). The gain is
A
V
g
M
R
L
8 I
C
R
L
2kT
0.002R
L
and can easily be reduced from a nominal of 10,000 by an external
shunt resistance from Pin 9 to ground, as shown in Figure 7.
In addition to DC gain control, the compensation terminal is also the
place for AC phase compensation. The frequency response curves
of Figure 7 show the uncompensated amplifier with a single pole at
approximately 200Hz and a unity gain crossover at 5MHz.
Typically, most output filter designs will introduce one or more
additional poles at a significantly lower frequency. Therefore, the
best stabilizing network is a series RC combination between Pin 9
and ground which introduces a zero to cancel one of the output filter
poles. A good starting point is 50k
plus 0.001
μ
F.
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