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參數(shù)資料
| 型號(hào)： | SG-8002JF3.6800M-PHML0 |
| 廠商： | EPSON TOYOCOM CORP |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 3.68 MHz, CMOS OUTPUT |
| 封裝： | PLASTIC PACKAGE-4 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 585K |
| 代理商： | SG-8002JF3.6800M-PHML0 |
http://www.epsontoyocom.co.jp
Crystal oscillator
Epson Toyocom
SG / HG-8002 series_
Jitter specifications and characteristics chart
■
PLL-PLL connection
Because we use a PLL technology, there are a few cases that the jitter value will increase when SG-8002 is connected to another
PLL-oscillator.
In our experience, we are unable to recommend these products for the applications such as telecom carrier use or analog video
clock use. Please be careful checking in advance for these application (Jitter specification is Max.250 ps/CL=
1
5 pF)
Jitter Specifications
Supply
Voltage
1
50 ps Max.
Cycle to cycle
200 ps Max.
200 ps Max.
ST
/
SH
Peak to peak
250 ps Max.
Cycle to cycle
200 ps Max.
SC
/
PC
3.3 V
±
0.3 V
Peak to peak
250 ps Max.
■
Remarks on noise management for power supply line
We do not recommend inserting filters or other devices in the power supply line as the counter measure of EMI noise reduction.
This device insertion might cause high-frequency impedance high in the power supply line and it affects oscillator stable drive.
When this measure is required, please evaluate circuitry and device behavior in the circuit and verify that it will not affect oscillation.
Start up time (0 % V
CC
to 90 % V
CC
) of power source should be more than
1
50
μ
s.
■
SG-8002 series Characteristics chart
Model
Jitter Item
Specifications
Remarks
33 MHz
≤
f
0
≤
1
25 MHz, L_CMOS=
1
5 pF
1
.0 MHz
≤
f
0
< 33 MHz, L_CMOS=
1
5 pF
33 MHz
≤
f
0
≤
1
25 MHz, L_CMOS=
1
5 pF
1
.0 MHz
≤
f
0
< 33 MHz, L_CMOS=
1
5 pF
1
.0 MHz
≤
f
0
≤
1
25 MHz, L_CMOS=
1
5 pF
1
.0 MHz
≤
f
0
≤
1
25 MHz, L_CMOS=
1
5 pF
PT
/
PH
5.0 V
±
0.5 V
V
CC
=5.0 V
25 pF
Frequency(MHz)
0
Current consumption
(V
CC
=5.0V)
20
40
60
80
1
00
1
20
1
40
1
0
20
30
40
50
I
C
(
Frequency(MHz)
Stand-by Current
0
Disable Current
(V
CC
=5.0V)
20
40
60
80
1
00
1
20
1
40
1
0
20
30
40
50
I
_
(
V
CC
(V)
I
_
(
μ
A
2.5
3.0 3.5 4.0 4.5 5.0 5.5 6.0
1
0
20
30
40
50
Frequency(MHz)
0
Symmetry 5.0V TTL Level
20
40
60
80
1
00
1
20
1
40
40
45
50
55
60
S
0
Symmetry 3.3 V CMOS Level
20
40
Frequency(MHz)
60
80
1
00
1
20
1
40
40
45
50
55
60
S
0
Symmetry 5.0 V CMOS Level
20
40
Frequency(MHz)
60
80
1
00
1
20
1
40
40
45
50
55
60
S
0
Frequency(MHz)
Output load vs. Additional Current consumption
20
20
40
60
80
1
00
1
20
1
40
2
4
6
8
1
0
1
2
1
4
1
6
1
8
2.5
V
CC
(V)
Voltage coefficient [
V
CC
vs I_dis,I_std ]
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0.2
0.4
0.6
T
0.8
1
.0
1
.2
1
.4
1
.6
1
.8
2.0
R
1
0
Output Rise time (CMOS Level)
1
5 20 25 30 35 40 45
Load capacitance (pF)
Output Fall time (CMOS Level)
1
.0
1
.5
2.0
3.0
2.5
50 55
3.0
1
0
1
5 20 25 30 35 40 45
Load capacitance (pF)
1
.0
1
.5
2.0
2.5
F
50 55
1
0
Output Fall time (TTL Level)
20
25
30
1
.0
1
.5
2.0
Load c5
F
Output Rise time (TTL Level)
1
0
20
25
30
1
.0
1
.5
2.0
Load ca5
R
1
5 pF
50 pF
1
5 pF
30 pF
25 pF
1
5 pF
I_dis(Va)=Times(Va)×I_dis(5.0V)
I_std(Va)=Times(Va)×I_std(5.0V)
25 pF
1
5 pF
50 pF
30 pF
5.0 V
5.5 V
4.5 V
3.3 V
3.0 V
3.3 V
3.6 V
3.0 V
5.0 V
5.5 V
4.5 V
5.0 V
5.5 V
4.5 V
5.0 V
5.5 V
4.5 V
2.7 V
2.7 V
A
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