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參數(shù)資料
| 型號： | SED1500FOA |
| 元件分類： | 顯示控制器 |
| 英文描述： | 8 X 42 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP80 |
| 封裝： | QFP1-80 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 39K |
| 代理商： | SED1500FOA |
311
Timing Characteristics
° Read Operation
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Read cycle time
tRC
1000
—
ns
Access time 1
tA1
VIH = VOH = VDD – 2.0V
—
800
ns
Read input
→
tRD
VIL = VDL = VSS + 0.8V
—
800
ns
valid data output time
Read input
→
tRX
CL = 100 pF + 1 TTL
—
150
ns
data output time
Output disable time
tOTD
30
—
ns
Output hold time
tOHA
VSS = –5V
± 10%
20
_
—
ns
Address set pulse width
tAS
Ta = –20 to +75
°C
200
—
ns
Address hold time
tAH
100
—
ns
Port setup time
tPS
200
—
ns
° Write Operation
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Write recovery time
tWC
1000
—
ns
Write time
tW
800
—
ns
Port setup time
tPS
200
—
ns
Address setup time
tAW
VIN = VOH = VDD – 2.0V
0
—
ns
Write recovery time
tWR
VIL = VOL = VSS + 0.8V
200
—
ns
Output disable time
tODW
CL = 100 pF + 1 TTL
—
0
ns
Data setup time
tDS
VSS = –5V
± 10%
300
—
ns
Data hold time
tDH
Ta = –20 to 75
°C
100
—
ns
Address set pulse width
tAS
200
—
ns
Address hold time
tAH
100
—
ns
° Truth Table
CS
RD
WR
A0 to A3
A4 to A6
DIN
DOUT
Mode
D0 to D3
D4 to D7
D0 to D3
D4 to D7
H
**
*
High
Standby
impedance
L
H
Stable
Stable**
High
Data
Read
impedance
output
output**
cycle
L
H
L
Stable
Stable**
Stable
Stable**
High
Write
impedance
cycle
* “H” or “L”
** High impedance in 4-bit mode
SED1500 Series
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