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參數(shù)資料
| 型號： | SE567N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Tone decoder/phase-locked loop |
| 中文描述： | PHASE LOCKED LOOP, PDIP8 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大?。?/td> | 165K |
| 代理商： | SE567N |
Philips Semiconductors Linear Products
Product specification
NE/SE567
Tone decoder/phase-locked loop
April 15, 1992
406
DC ELECTRICAL CHARACTERISTICS
V +=5.0V; T
A
=25
°
C, unless otherwise specified.
SYM-
BOL
PARAMETER
TEST CONDITIONS
SE567
NE567
UNIT
Min
Typ
Max
Min
Typ
Max
Center frequency
1
f
O
Highest center frequency
f
O
Center frequency stability
2
500
500
kHz
ppm/
°
C
ppm/
°
C
%
-55 to +125
°
C
0 to +70
°
C
35
±
140
35
±
60
0
35
±
140
35
±
60
0
f
O
Center frequency distribution
f
O
100kHz
1
1.1R
1
C
1
-10
+10
-10
+10
f
O
Center frequency shift with supply
voltage
f
O
100kHz
1
1.1R
1
C
1
0.5
1
0.7
2
%/V
Detection bandwidth
BW
Largest detection bandwidth
f
O
100kHz
1
1.1R
1
C
1
12
14
16
10
14
18
% of f
O
BW
BW
Largest detection bandwidth skew
Largest detection bandwidth—
variation with temperature
Largest detection bandwidth—
variation with supply voltage
2
4
3
6
% of f
O
%/
°
C
V
I
=300mV
RMS
±
0.1
±
0.1
BW
V
I
=300mV
RMS
±
2
±
2
%/V
Input
R
IN
V
I
Input resistance
Smallest detectable input voltage
4
Largest no-output input voltage
4
Greatest simultaneous out-band
signal-to-in-band signal ratio
Minimum input signal to wide-band
noise ratio
Output
Fastest on-off cycling rate
“1” output leakage current
“0” output voltage
15
20
20
15
+6
25
25
15
20
20
15
+6
25
25
k
I
L
=100mA, f
I
=f
O
I
L
=100mA, f
I
=f
O
mV
RMS
mV
RMS
dB
10
10
B
n
=140kHz
-6
-6
dB
f
O
/20
0.01
0.2
0.6
30
150
f
O
/20
0.01
0.2
0.6
30
150
V
8
=15V
I
L
=30mA
I
L
=100mA
R
L
=50
R
L
=50
25
0.4
1.0
25
0.4
1.0
μ
A
V
V
ns
ns
t
F
t
R
General
Output fall time
3
Output rise time
3
CC
Operating voltage range
4.75
9.0
4.75
9.0
V
Supply current quiescent
6
8
7
10
mA
Supply current—activated
R
L
=20k
11
13
12
15
mA
t
PD
NOTES:
1. Frequency determining resistor R
1
should be between 2 and 20k
2. Applicable over 4.75V to 5.75V. See graphs for more detailed information.
3. Pin 8 to Pin 1 feedback R
L
network selected to eliminate pulsing during turn-on and turn-off.
4. With R
2
=130k
from Pin 1 to V+. See Figure 1.
Quiescent power dissipation
30
35
mW
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