![](http://datasheet.mmic.net.cn/260000/TMS370C736AFNT_datasheet_15975231/TMS370C736AFNT_28.png)
T
8
S
T
2
P
Table 16. TMS370 Family Opcode/Instruction Map
(Continued)
MSN
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
C
JNV
ra
2/5
MPY
Rs,A
2/46
MPY
#n,A
2/45
MPY
Rs,B
2/46
MPY
Rs,Rd
3/48
MPY
#n,B
2/45
MPY
B,A
1/47
MPY
#n,Rs
3/47
BR
lab
3/9
BR
*Rp
2/8
BR
*lab[B]
3/11
RR
A
1/8
RR
B
1/8
RR
Rd
2/6
TRAP
3
1/14
POP
ST
1/8
L
S
N
D
JGE
ra
2/5
CMP
Rs,A
2/7
CMP
#n,A
2/6
CMP
Rs,B
2/7
CMP
Rs,Rd
3/9
CMP
#n,B
2/6
CMP
B,A
1/8
CMP
#n,Rd
3/8
CMP
& lab,A
3/11
CMP
*Rp,A
2/10
CMP
*lab[B],A
3/13
RRC
A
1/8
RRC
B
1/8
RRC
Rd
2/6
TRAP
2
1/14
LDSP
1/7
E
JG
ra
2/5
DAC
Rs,A
2/9
DAC
#n,A
2/8
DAC
Rs,B
2/9
DAC
Rs,Rd
3/11
DAC
#n,B
2/8
DAC
B,A
1/10
DAC
#n,Rd
3/10
CALL
lab
3/13
CALL
*Rp
2/12
CALL
*lab[B]
3/15
RL
A
1/8
RL
B
1/8
RL
Rd
2/6
TRAP
1
1/14
STSP
1/8
F
JLO
ra
2/5
DSB
Rs,A
2/9
DSB
#n,A
2/8
DSB
Rs,B
2/9
DSB
Rs,Rd
3/11
DSB
#n,B
2/8
DSB
B,A
1/10
DSB
#n,Rd
3/10
CALLR
lab
3/15
CALLR
*Rp
2/14
CALLR
*lab[B]
3/17
RLC
A
1/8
RLC
B
1/8
RLC
Rd
2/6
TRAP
0
1/14
NOP
1/7
Second byte of two-byte instructions (F4xx):
F4
8
MOVW
*n[Rn]
4/15
DIV
Rn.A
3/14-63
F4
9
JMPL
*n[Rn]
4/16
Legend:
*
&
#
#16 =
lab =
n
Pd =
Pn =
Ps =
ra
Rd =
Rn =
Rp =
Rpd=
Rps =
Rs =
=
=
=
Indirect addressing operand prefix
Direct addressing operand prefix
immediate operand
immediate 16-bit number
16-label
di t 8 bit
immediate 8-bit number
Peripheral register containing destination type
Peripheral register
Peripheral register containing source byte
Peri heral register containing source byte
Relative address
Register containing destination type
Register file
Register pair
Destination register pair
Source Register pair
Register containing source byte
F4
A
MOV
*n[Rn],A
4/17
F4
B
MOV
A,*n[Rn]
4/16
=
F4
C
BR
*n[Rn]
4/16
=
F4
D
CMP
*n[Rn],A
4/18
F4
E
CALL
*n[Rn]
4/20
F4
F
CALLR
*n[Rn]
4/22
All conditional jumps (opcodes 01-0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions
have a relative address as the last operand.