- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368672 > SE370C712BJDT 8-BIT MICROCONTROLLER PDF資料下載
參數(shù)資料
| 型號(hào)： | SE370C712BJDT |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 40/48頁 |
| 文件大?。?/td> | 711K |
| 代理商： | SE370C712BJDT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當(dāng)前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
TMS370Cx36
8-BIT MICROCONTROLLER
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997
40
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
external clocking requirements for clock divided by 4 (see Note 9 and Figure 16)
NO.
PARAMETER
MIN
MAX
UNIT
1
tw(Cl)
tr(Cl)
tf(CI)
td(CIH-SCL)
CLKIN
Pulse duration, XTAL2/CLKIN (see Note 10)
20
ns
2
Rise time, XTAL2/CLKIN
30
ns
3
Fall time, XTAL2/CLKIN
30
ns
4
Delay time, XTAL2/CLKIN rise to SYSCLK fall
100
ns
Crystal operating frequency
Internal system clock operating frequency
2
20
MHz
SYSCLK
0.5
5
MHz
SYSCLK = CLKIN/4
NOTES:
9. For VIL and VIH, refer to recommended operating conditions.
10. This pulse may be either a high pulse, as illustrated below, which extends from the earliest valid high to the final valid high in an
XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.
XTAL2/CLKIN
3
2
1
4
SYSCLK
Figure 16. External Clock Timing for Divide-by-4
external clocking requirements for clock divided by 1 (PLL) (see Note 9 and Figure 17)
NO.
1
PARAMETER
MIN
20
MAX
UNIT
ns
tw(Cl)
tr(Cl)
tf(CI)
td(CIH-SCH)
CLKIN
Pulse duration, XTAL2/CLKIN (see Note 10)
2
Rise time, XTAL2/CLKIN
30
ns
3
Fall time, XTAL2/CLKIN
30
ns
4
Delay time, XTAL2/CLKIN rise to SYSCLK rise
100
ns
Crystal operating frequency
Internal system clock operating frequency
2
5
MHz
SYSCLK
2
5
MHz
SYSCLK = CLKIN/1
NOTES:
9. For VIL and VIH, refer to recommended operating conditions.
10. This pulse can be either a high pulse, as illustrated below, which extends from the earliest valid high to the final valid high in an
XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.
4
3
2
1
XTAL2/CLKIN
SYSCLK
Figure 17. External Clock Timing for Divide-by-1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SE370C732AFZT | 8-BIT MICROCONTROLLER |
| SE370C736AFZT | 8-BIT MICROCONTROLLER |
| SE370C742AJCT | 8-BIT MICROCONTROLLER |
| SE370C742AJDT | 8-BIT MICROCONTROLLER |
| SE370C742FZA | 8-BIT MICROCONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SE370C712BYYZ | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS370 MICROCONTROLLER FAMILY DATA BOOK |
| SE370C722 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT MICROCONTROLLER |
| SE370C722FZT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT MICROCONTROLLER |
| SE370C722JCT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT MICROCONTROLLER |
| SE370C722JDS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT MICROCONTROLLER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。