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參數(shù)資料
| 型號： | SDC-634ST-H3AR |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP27 |
| 封裝： | 3.125 X 2.625 INCH, 0.430 INCH HEIGHT, MODULE-28/27 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 464K |
| 代理商： | SDC-634ST-H3AR |
Data changes on the leading edge of the CB pulse, and data can
be transferred 0.5 sec after the leading edge.
The simplest method of interfacing with a computer is to transfer
data at a fixed time interval after the Inhibit is applied. The con-
verter will ignore an Inhibit during the “busy” interval until that
interval is over. Timing is as follows: (a) apply the Inhibit, (b) wait
0.5 sec, (c) transfer the data, (d) release the Inhibit. The Inhibit
line has no effect on converter tracking.
SIGNAL INPUTS
To prevent damage to the inputs, the maximum steady-state volt-
age should not exceed the specified input voltage by more than
30%.
ACCOMMODATING NON-STANDARD INPUT
VOLTAGES (A ONLY)
The signal and reference input levels can be resistively scaled to
accommodate non-standard voltages, see FIGURE 3. Select a
converter that is the next lower standard voltage, and the voltage
is then scaled up by using resistors in series with the synchro
and/or reference inputs.
For a synchro input (SDC), a resistor R
SIG
is added in series
with S1, S2 and S3 which is determined as follows:
R
SIG = 1.1k (New L-L Voltage – Standard Unit L-L Voltage)
That is, 1.1k for each volt above the design voltage level of the
standard unit.
Example: An SDC-634A-L (11.8 V) is to be used at 50 V L-L.
R
SIG = 1.1k (50 – 11.8) = 42.2k
The closest available high grade resistor with a low temperature
coefficient of resistance should be used, and the three resistors
should be as closely matched to each other as possible. In gen-
eral, a 0.1% difference will introduce 1.7 arc minutes of addition-
al error due to the effect on SIN/COS ratio relationship.
The ABSOLUTE value of the resistor is not critical.
In the case of the RESOLVER version (RDC), the equation is:
R
SIG = 2.2k (New L-L Voltage – Standard Unit L-L Voltage)
The calculated resistors are connected in series with S1 and S2
respectively. Note only two resistors are required. The required
resistance matching and its effect on accuracy, is the same as for
a synchro input, see FIGURE 3. The Reference Voltage is treat-
ed in the same manner, but the value is not critical.
RREF = 2.8k (New Reference – Standard Reference)
For this use a 10% tolerance resistor is adequate.
3
UNITS
Hz
1/s
rps
°/s2
msec
60 HZ
47 - 1,000
15
1,100
0.1
7,600
33
16.3
28.5
24
370
500
10
12
14
16
10
12
14
16
7.1
6
93
600
1.8
1.5
23
900
0.45
0.37
5.8
2,200
192
160
17,000
90
48
40
4,220
100
12
10
1,050
140
3
2.5
260
320
400 HZ
360 - 1,000 (ST to 5,000)
100
48,000
1
48,000
220
110
RESOLUTION
Bandwidth (non F carrier)
Carrier Frequency Range
Bandwidth (Closed Loop)
Ka
A1
A2
A
B
Tracking Rate (rps)
Typical
Minimum
Acceleration (1 LSB lag)
Settling Time (179° step, max)
TABLE 2. SDC-630/632/634 A/ST DYNAMIC CHARACTERISTICS
{
NONSTANDARD
LINE-TO-LINE
LEVEL
SDC-630A
NONSTANDARD
REFERENCE
LEVEL
R
S1
S2
S3
R
SIG
REF
SIG
FIGURE 3. SDC-630/632/634 A/ST NON-STANDARD
INPUT LEVEL SCALING
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SDC-634-ST-H-3-R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchro-to-Digital Converter |
| SDC-634-ST-I-1-AR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchro-to-Digital Converter |
| SDC-634-ST-I-1-R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchro-to-Digital Converter |
| SDC-634-ST-I-3-AR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchro-to-Digital Converter |
| SDC-634-ST-I-3-R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchro-to-Digital Converter |
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