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參數(shù)資料
| 型號： | SDC-14616-202Y |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| 封裝： | 1.700 X 0.780 INCH, 0.210 INCH HEIGHT, DDIP-36 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 278K |
| 代理商： | SDC-14616-202Y |
4
Data Device Corporation
www.ddc-web.com
SDC-14610/15 Series
K-05/04-0
THEORY OF OPERATION
The SDC-14610/15 Series of converters are based upon a sin-
gle chip CMOS custom monolithic. They are implemented using
the latest IC technology which merges precision analog circuitry
with digital logic to form a complete high performance tracking
resolver-to-digital converter.
Figure 1 is the Functional Block Diagram of the SDC-14610/15
Series. The converter operates with ±5VDC power supplies.
Analog signals are referenced to analog ground, which is at
ground potential. The converter is made up of three main sec-
tions; an input front-end, a converter, and a digital interface. The
converter front-end differs for synchro, resolver and direct inputs.
An electronic Scott-T is used for synchro inputs, a resolver con-
ditioner for resolver inputs and a sine and cosine voltage follow-
er for direct inputs. These amplifiers feed the high accuracy
Control Transformer (CT). Its other input is the 14-bit digital angle
f. Its output is an analog error angle, or difference angle, between
the two inputs. The CT performs the ratiometric trigonometric
computation of SINqCOSf - COSqSINf = SIN(q - f) using ampli-
fiers, switches, logic and capacitors in precision ratios.
The converter accuracy is limited by the precision of the comput-
ing elements in the CT. In these converters, ratioed capacitors
are used in the CT instead of more conventional precision ratioed
resistors. Capacitors used as computing elements with op-amps
need to be sampled to eliminate voltage drifting. Therefore, the
circuits are sampled at a high rate to eliminate this drifting and at
the same time to cancel out the op-amp offsets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The DC error is
integrated yielding a velocity voltage which, in turn, drives a volt-
age controlled oscillator (VCO). This VCO is an incremental inte-
grator (constant voltage input to position rate output) which,
together with the velocity integrator, forms a type II servo feed-
back loop. A lead in the frequency response is introduced to sta-
bilize the loop and another lag at higher frequency is introduced
to reduce the gain and ripple at the carrier frequency and above.
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined
from its functional block diagram and its Bode plots (open and
closed loop); these are shown in figureS 1 and 2 respectively.
GENERAL SETUP CONSIDERATIONS
The following recommendations should be considered when
connecting the SDC-14610/15 Series converters:
1) Power supplies are ±5VDC. For lowest noise performance
it is recommended that a 0.1 F or larger cap be connected
from each supply to ground near the converter package.
2) Direct inputs are referenced to AGND.
3) Connect pin 5 (GND) to pin 6 (AGND) close to the hybrid.
-12
db/oct
GAIN = 4
BA
2A
-6 db/oct
10B
ω (rad/sec)
2A
2 2 A
ω (rad/sec)
f
= BW =
3db
2 A (Hz)
π
CLOSED LOOP
OPEN LOOP
- GAIN = 0.4
(B=A/2)
(CRITICALLY DAMPED)
FIGURE 2. BODE PLOTS
The open loop transfer function is as follows:
S
2
( S + 1)
10B
where A is the gain coefficient
and B is the frequency of lead compensation
Open Loop Transfer Function =
A
2
( S + 1)
B
- Integrator Gain =
volts per second per volt
Ri Ci
1
- VCO Gain =
LSBs per second per volt
1.25 Rv Cv
1
- Error Gradient = 0.011 volts per LSB (CT + Error Amp + Demod)
The components of gain coefficient are error gradient, integrator
gain, and VCO gain. These can be broken down as follows:
TABLE 1. SDC 14610/15 SPECIFICATIONS (CONT.)
PARAMETER
UNIT
VALUE
PHYSICAL
CHARACTERISTICS
Size
Weight
1.70 x 0.78 x 0.21
(43.2 x 19.8 x 5.3)
0.66(18.7)
in
(mm)
oz(g)
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