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參數(shù)資料
| 型號： | SDC-14611-202S |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| 封裝： | 1.700 X 0.780 INCH, 0.210 INCH HEIGHT, DDIP-36 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 278K |
| 代理商： | SDC-14611-202S |
5
Data Device Corporation
www.ddc-web.com
SDC-14610/15 Series
K-05/04-0
INHIBIT AND ENABLE TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being trans-
ferred. Application of an Inhibit signal does not interfere with the
continuous tracking of the converter. As shown in figure 3, angu-
lar output data is valid 500 nanoseconds maximum after the
application of the low-going inhibit pulse.
Output angle data is enabled onto the tri-state data bus in six
bytes. The Enable MSB (EM-A, EM-B, or EM-C) is used for the
most significant 8 bits and Enable LSB (EL-A, EL-B, or EL-C) is
used for the least significant bits. As shown in figure 4, output
data is valid 150 nanoseconds maximum after the application of
a low-going enable pulse. The tri-state data bus returns to the
high impedance state 100 nanoseconds maximum after the ris-
ing edge of the enable signal.
BIT, BUILT-IN-TEST (“T” OPTION)
This output is a logic line that will flag an internal fault condition,
or LOS (Loss-Of-Signal). The internal fault detector monitors the
internal error and, when it exceeds ±100 LSBs, will set the line
to a logic 0; this condition will occur during a large-step input and
will reset to a logic 1 after the converter settles out. (The error
voltage is filtered with a 500 s filter) BIT will set for an overve-
locity condition because the converter loop can’t maintain
input/output sync. BIT will also be set if a total LOS (loss of all
signals) occurs or an LOR (loss of reference - “S” option only)
occurs.
;
ENABLE
150 ns MAX
DATA
VALID
100 ns MAX
HIGH Z
;;;;;;
DATA
VALID
500 ns MAX
INHIBIT
FIGURE 3. INHIBIT TIMING
FIGURE 4. ENABLE TIMING
NO FALSE 180° HANGUP
This feature eliminates the “false 180° reading” during instanta-
neous 180° step changes; this condition most often occurs when
the input is “electronically switched” from a digital-to-synchro
converter. If the “MSB” (or 180° bit) is “toggled” on and off, a con-
verter without the “false 180° reading” feature may fail to
respond.
The condition is artificial, as a “real” synchro or resolver cannot
change its output 180° instantaneously. The condition is most
often noticed during wraparound verification tests, simulations,
or troubleshooting.
SYNTHESIZED REFERENCE
The synthesized reference section (“S” option) eliminates errors
due to phase shift between the reference and signal inputs.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage (e)
in the converter. Due to the inductive nature of synchros and
resolvers, their output signals lead the reference input signal (RH
and RL). When an uncompensated reference signal is used to
demodulate the control transformer’s output, quadrature voltages
are not completely eliminated. As shown in FIGURE 1, the con-
verter synthesizes its own internal reference signal based on the
SIN and COS signal inputs. Therefore, the phase of the synthe-
sized (internal) reference is determined by the signal input, result-
ing in reduced quadrature errors. The synthesized reference cir-
cuit also eliminates the 180 degree false error null hang up.
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