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參數(shù)資料
| 型號： | SDC-14603T-842S |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DMA28 |
| 封裝： | DDIP-28 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 237K |
| 代理商： | SDC-14603T-842S |
THEORY OF OPERATION
The SDC-14600/05 Series of converters are based upon a sin-
gle chip CMOS custom monolithic. They are implemented using
the latest IC technology which merges precision analog circuitry
with digital logic to form a complete high performance tracking
resolver to digital converter.
FIGURE 1 is the Functional Block Diagram of SDC-14600/05
Series. The converter operates with +5 Vdc power supplies.
Analog signals are referenced to analog ground, which is at
ground potential. The converter is made up of three main sec-
tions; an input front-end, a converter, and a digital interface. The
converter front-end differs for synchro, resolver and direct inputs.
An electronic Scott-T is used for synchro inputs, a resolver con-
ditioner for resolver inputs and a sine and cosine voltage follow-
er for direct inputs. These amplifiers feed the high accuracy
Control Transformer (CT). Its other input is the 14 bit digital
angle
φ. Its output is an analog error angle, or difference angle,
between the two inputs. The CT performs the ratiometric trigono-
metric computation of SIN
θCOSφ - COSθSINφ = SIN(θ-φ) using
amplifiers, switches, logic and capacitors in precision ratios.
The converter accuracy is limited by the precision of the com-
puting elements in the CT. In these converters ratioed capacitors
are used in the CT, instead of the more conventional precision
ratioed resistors. Capacitors used as computing elements with
op-amps need to be sampled to eliminate voltage drifting.
Therefore, the circuits are sampled at a high rate to eliminate this
drifting and at the same time to cancel out the op-amp offsets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The dc error is inte-
grated yielding a velocity voltage which in turn drives a voltage
controlled oscillator (VCO). This VCO is an incremental integra-
tor (constant voltage input to position rate output) which togeth-
er with the velocity integrator forms a type II servo feedback
loop. A lead in the frequency response is introduced to stabilize
the loop and another lag at higher frequency is introduced to
reduce the gain and ripple at the carrier frequency and above.
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined
from its functional block diagram and its bode plots (open and
closed loop); These are shown in FIGURES 1 and 2.
The open loop transfer function is as follows:
S
A2
+1
B
(
)
Open Loop Transfer Function =
S
S2
+1
10B
(
)
where A is the gain coefficient
and B is the frequency of lead compensation
The components of gain coefficient are error gradient, integrator
gain, and VCO gain. These can be broken down as follows:
- Error Gradient = 0.011 volts per LSB (CT+Error Amp+Demod)
1
- Integrator gain =
volts per second per volt
RiCi
1
- VCO Gain =
LSBs per second per volt
1.25RvCv
GENERAL SETUP CONSIDERATIONS
The following recommendations should be considered when
connecting the SDC-14600/05 Series converters:
1) Power supplies are ±5 Vdc. For lowest noise performance it is
recommended that a 0.1 F or larger cap be connected from
each supply to ground near the converter package.
2) Direct inputs are referenced to A GND.
INHIBIT AND ENABLE TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being trans-
ferred. Application of an Inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 3,
angular output data is valid 500 nanoseconds maximum after the
application of the low-going inhibit pulse.
Output angle data is enabled onto the tri-state data bus in four
bytes. The Enable MSB (EM A or EM B) is used for the most sig-
nificant 8 bits and Enable LSB (EL A or EL B) is used for the
least significant bits. As shown in FIGURE 4, output data is valid
150 nanoseconds maximum after the application of a low-going
enable pulse. The tri-state data bus returns to the high imped-
ance state 100 nanoseconds maximum after the rising edge of
the enable signal.
3
-12
db/oct
GAIN = 4
BA
2A
-6 db/oct
10B
ω (rad/sec)
2A
2 2 A
ω (rad/sec)
f
= BW =
3db
2 A (Hz)
π
CLOSED LOOP
OPEN LOOP
- GAIN = 0.4
(B=A/2)
(CRITICALLY DAMPED)
FIGURE 2. BODE PLOTS
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