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參數(shù)資料
| 型號(hào)： | SDC-14567-501 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| 封裝： | 1.900 X 0.780 INCH, 0.210 INCH HEIGHT, DOUBLE WIDTH, KOVAR, DIP-36 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 196K |
| 代理商： | SDC-14567-501 |
(LSBs) are enabled by the signal EL. Outputs are valid (logic “1”
or “0”) 150 ns max after setting EM or EL low, and are high
impedance within 100 ns max of setting EM or EL high. Both EM
and EL are internally pulled-up to +5 V at 30 A max.
The inhibit (INH) input locks the transparent latch so the bits will
remain stable while data is being transferred (see FIGURE 1).
The output is stable 0.5 s after INH is driven to logic “0”, see
FIGURE 4. A logic “0” at the T input latches the data, and a logic
“1” applied to T will allow the bits to change. The inhibit transpar-
ent latch prevents the transmission of invalid data when there is
an overlap between CB and INH. While the counter is not being
updated, CB is at logic “0” and the INH latch is transparent.
When CB goes to logic “1” the INH latch is locked. If CB occurs
after INH has been applied, the latch will remain locked and its
data will not change until CB returns to logic “0”; if INH is applied
during CB, the latch will not lock until the CB pulse is over. The
purpose of the 50 ns delay is to prevent a race condition between
CB and INH where the up-down counter begins to change as an
INH is applied. Whenever an input angle change occurs, the
converter changes the digital angle in 1 LSB steps and gener-
ates a converter busy pulse. Output data change is initiated by
the leading edge of the CB pulse, delayed by 50 ns, nominal.
Valid data is available at the outputs 0.2 s after the leading edge
of CB, see FIGURE 5.
RESOLUTION CONTROL
Resolution control is via two logic inputs, A and B. The resolution
can be changed during converter operation so the appropriate
resolution and velocity dynamics can be changed as needed. To
ensure that no race conditions exist between counting and
changing the resolution, inputs A and B are latched internally on
the trailing edge of CB, as illustrated in FIGURE 6.
Digital angle outputs are buffered and are provided in a two byte
format. The first byte always contains the MSBs (bits 1-8) and is
enabled by placing EM (pin 26) to logic “0”. Depending on the
user-programmed resolution, the second byte will have bits 9
through 10, 9 through 12, or 9 through 14, while operating at 10-,
12-, or 14-bit resolution, respectively. Placing EL (pin 25) to logic “0”
enables the second byte, the LSBs. A logic “0” will be present on
all the unused least significant bits. TABLE 2 lists the deg/bit for
the digital angle outputs.
BUILT-IN-TEST
The Built-ln-Test output (BIT) monitors the level of error (D) from
the demodulator. D represents the difference in the input and
output angles and ideally should be zero; if it exceeds approxi-
mately 65 LSBs (of the selected resolution) the logic level at BIT
will change from a logic 1 to logic 0. This condition will occur dur-
ing a large step and reset after the converter settles out. BIT will
also change to logic 0 for an over-velocity condition, because the
converter loop cannot maintain input-output or if the converter
malfunctions where it cannot maintain the loop at a null. BIT will
also be set if a total Loss-of-Signal (LOS) and/or a Loss-of-
Reference (LOR) occurs.
DYNAMIC PERFORMANCE
A Type II servo loop (Kv =
∞) and very high acceleration constants
give the SDC-14560 superior dynamic performance, as listed in
TABLE 2. If the power supply voltages are not the ±15 V DC nom-
inal values, the specified input rates will increase or decrease in
proportion to the fractional change in voltage. A Control Loop
Block Diagram is shown in FIGURE 7, and an Open Loop Bode
Plot is shown in FIGURE 8. The values of the transfer function
coefficients are shown in TABLE 3.
An inhibit input, regardless of its duration, does not affect the con-
verter update. A simple method of interfacing to a computer asyn-
chronously to CB is: (A) apply the inhibit, (B) wait 0.5 s min., (C)
transfer the data and (D) release the inhibit.
5
,,,
,,
14B
0
s MIN
CB
0.1
s MIN
FIGURE 6. RESOLUTION CONTROL TIMING DIAGRAM
,
DEPENDS ON d
φ/dt
0.4-1.0
s
CB
0.2
s
DATA
VALID
6.1
s MIN
FIGURE 5. CONVERTER BUSY TIMING DIAGRAM
,,
DATA
VALID
0.5
s
ASYNCHROUS TO CB
INH
FIGURE 4. INHIBIT TIMING DIAGRAM
TABLE 2. DIGITAL ANGLE OUTPUTS
BIT
DEG/BIT
MIN/BIT
1 MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
180.0
90.0
45.0
22.5
11.25
5.625
2.813
1.406
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
10800.0
5400.0
2700.0
1350.0
675.0
337.5
168.75
84.38
42.19
21.09
10.55
5.27
2.64
1.32
0.66
0.33
Note: EM enables the MSBs and EL enables the LSBs.
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| SDC-14567-502Q | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
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| SDC-14567-502W | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| SDC-14567-502Y | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| SDC-14567-502Z | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
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