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參數(shù)資料
| 型號： | SDC-14563-572L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| 封裝： | 1.900 X 0.780 INCH, 0.210 INCH HEIGHT, DOUBLE WIDTH, KOVAR, DIP-36 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 196K |
| 代理商： | SDC-14563-572L |
As long as the converter maximum tracking rate is not exceed-
ed, there will be no lag in the converter output. If a step input
occurs, as when the power is initially applied, the response will
be critically damped. FIGURE 9 shows the response to a step
input. After initial slewing at the maximum tracking rate of the
converter, there is one overshoot (which is inherent in a Type II
servo). The overshoot settling to final value is a function of the
small signal settling time. For Velocity output, the simple filter
shown in FIGURE 10 will eliminate the one overshoot for step
velocity input and will filter the carrier frequency ripple.
ANALOG OUTPUTS
The analog outputs are velocity (VEL) and AC error (e). Both out-
puts can swing ±10 V min. with respect to ground when the volt-
age level of the ±15 V power supplies are 15 V. The output level
range changes proportionally if the power supply levels are not
at 15 V.
The AC error, e, is proportional to the error (
θ - φ) with a scaling
of 50 mV/LSB (10-bit mode), 25 mV/LSB (12-bit mode) 12.5 mV/
LSB (14-bit mode), and 6.3 mV/LSB (16-bit mode). Velocity out-
put characteristics are listed in TABLE 4.
6
OUTPUT
91k
VEL
(pin 23)
0.1 F
RC = 1/A
FIGURE 10. VELOCITY FILTER
ERROR PROCESSOR
INPUT
θ
Open Loop Transfer function = Output
WHERE:
2
A = A A
1
2
VELOCITY
OUT
DIGITAL
POSITION
OUT
(
φ)
VCO
CT
S
A
+ 1
1
B
S
+ 1
10B
H = 1
S
A
+ 1
1
B
2
S
+ 1
10B
+
-
e
A
2
S
2.75
4
BA
BW
ω (rad/sec)
OVERSHOOT
SMALL SIGNAL
SETTLING TIME
MAX SLOPE EQUALS
TRACKING RATE (SLEW RATE)
θ2
θ1
SETTLING TIME
FIGURE 9. RESPONSE TO A STEP INPUT
FIGURE 8. OPEN LOOP BODE PLOT
FIGURE 7. CONTROL LOOP BLOCK DIAGRAM
TABLE 3. DYNAMIC CHARACTERISTICS
PARAMETER
UNITS
BANDWIDTH
400 HZ
60 HZ
RESOLUTION
Input Frequency
Tracking Rate
Bandwidth
Ka
A1
A2
A
B
acc-1 LSB lag
Settling Time
BITS
Hertz
RPS min
Hertz
1/sec2 nom
1/sec nom
Deg/sec2 nom
ms max
10
12
14
16
360-1000
160
40
10
2.5
220
*
54
*
81.2k
*
12500 *
2.0
*
0.31
*
40k
*
40k
*
285
*
112
*
52
*
52
*
28.4k
7.1k
275
69
160
300
800
10
12
14
16
47-1000
40
10
2.5
0.61
40
*
14
*
3k
*
780
*
0.29
*
0.078 *
10k
*
10k
*
55
*
28
*
13
*
13
*
1k
264
17.2
4.3
350
550
1400
3400
Note: * means the same as value to the left.
相關(guān)PDF資料 |
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| SDC-14563-572W | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| SDC-14563-572Y | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| SDC-14563-572Z | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| SDC-14563-572 | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| SDC-14563-574K | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
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